can halt
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@ -12,6 +12,7 @@ namespace ZYM {
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const int kROBSize = 32;
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const int kTotalRegister = 32;
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struct CentralScheduleUnit_Input {
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dark::Wire<8> a0;
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dark::Wire<1> reset;
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// data from load store queue
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dark::Wire<6> load_store_queue_emptyspace_receiver;
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@ -262,7 +263,8 @@ struct CentralScheduleUnit
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}
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ROB_next_remain_space++;
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if (record.instruction == 0x0ff00513) {
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halt_signal <= 0b100000000;
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halt_signal <= (0b100000000 | static_cast<max_size_t>(a0));
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std::cerr << "halting with code " << std::dec << int(halt_signal.peek()) << std::endl;
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}
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}
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}
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@ -281,23 +283,28 @@ struct CentralScheduleUnit
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record.resulting_register_value <= res_data;
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if (!bool(record.resulting_PC_ready)) {
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record.resulting_PC <= res_PC;
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if (res_PC != static_cast<max_size_t>(record.resulting_PC)) {
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if (res_PC != static_cast<max_size_t>(record.resulting_PC) &&
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(static_cast<max_size_t>(record.instruction) & 0x7F) != 0b1100111) {
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record.PC_mismatch_mark <= 1;
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}
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record.resulting_PC_ready <= 1;
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if ((static_cast<max_size_t>(record.instruction) & 0x7F) == 0b1100111) {
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has_predicted_PC <= 1;
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predicted_PC <= record.resulting_PC;
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predicted_PC <= res_PC;
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std::cerr << "The jalr instruction is committed, now predicted_PC is " << std::hex << std::setw(8)
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<< std::setfill('0') << std::uppercase << predicted_PC.peek() << std::endl;
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}
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}
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record.state <= 3;
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}
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}
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};
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std::cerr << "csu is listening data from memory" << std::endl;
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if (static_cast<max_size_t>(mem_status_receiver) == 0b10) {
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process_data(static_cast<max_size_t>(completed_memins_ROB_index),
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static_cast<max_size_t>(completed_memins_read_data), 0);
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}
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std::cerr << "csu is listening data from alu" << std::endl;
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if (static_cast<max_size_t>(alu_status_receiver) == 0b10) {
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process_data(static_cast<max_size_t>(completed_aluins_ROB_index),
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static_cast<max_size_t>(completed_aluins_result),
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@ -383,7 +390,7 @@ struct CentralScheduleUnit
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break;
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case 0b1100111:
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// jalr
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std::cerr<<"encounter jalr"<<std::endl;
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std::cerr << "encounter jalr" << std::endl;
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ROB_records[tail].resulting_PC_ready <= 0;
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has_predicted_PC <= 0;
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break;
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@ -427,23 +434,39 @@ struct CentralScheduleUnit
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}
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// provide the potentially missing data for instruction issued last cycle
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if (bool(has_instruction_issued_last_cycle)) {
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std::cerr << "CSU is processing potentially missing data for instruction issued last cycle" << std::endl;
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uint8_t rs1 = static_cast<max_size_t>(this->decoded_rs1);
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uint8_t found_rs1 = 0;
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uint32_t rs1_v;
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uint8_t rs2 = static_cast<max_size_t>(this->decoded_rs2);
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uint8_t found_rs2 = 0;
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uint32_t rs2_v;
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for (uint32_t ptr = static_cast<max_size_t>(ROB_head); ptr != static_cast<max_size_t>(ROB_tail);
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for (uint32_t ptr = static_cast<max_size_t>(ROB_head);
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ptr != static_cast<max_size_t>(ROB_tail) && (ptr + 1) % kROBSize != static_cast<max_size_t>(ROB_tail);
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ptr = (ptr + 1) % kROBSize) {
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if (ROB_records[ptr].state.peek() == 3) {
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if (static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs1) {
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if (bool(ROB_records[ptr].has_resulting_register) &&
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static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs1) {
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rs1_v = ROB_records[ptr].resulting_register_value.peek();
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found_rs1 = 1;
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std::cerr << "matching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr << " rs1_v=" << std::hex
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<< std::setw(8) << std::setfill('0') << rs1_v << std::endl;
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}
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if (static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs2) {
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if (bool(ROB_records[ptr].has_resulting_register) &&
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static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs2) {
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rs2_v = ROB_records[ptr].resulting_register_value.peek();
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found_rs2 = 1;
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}
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} else {
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if (bool(ROB_records[ptr].has_resulting_register) &&
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static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs1) {
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found_rs1 = 0;
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std::cerr << "dematching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr << std::endl;
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}
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if (bool(ROB_records[ptr].has_resulting_register) &&
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static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs2) {
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found_rs2 = 0;
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}
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}
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}
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this->rs1_is_in_ROB <= found_rs1;
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