ZYM/RISC-V-Simulator
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finish rough design, ready to write work() function

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This commit is contained in:
ZhuangYumin
2024-07-31 02:32:02 +00:00
parent e0d6a82066
commit 45288e1c36
6 changed files with 202 additions and 34 deletions
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3
include/alu.h
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@ -7,6 +7,7 @@ struct ALU_Input {
dark::Wire<32> operand1;
dark::Wire<32> operand2;
dark::Wire<5> request_ROB_index;
dark::Wire<32> request_PC;
};
struct ALU_Output {
dark::Register<2> alu_status;
@ -22,5 +23,5 @@ struct ALU : public dark::Module<ALU_Input, ALU_Output> {
// Update function
}
};
}
} // namespace ZYM
#endif

18
include/csu.h
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@ -27,10 +27,10 @@ struct CentralScheduleUnit_Input {
dark::Wire<32> completed_aluins_result;
dark::Wire<32> completed_alu_resulting_PC;
// receive data from register file
dark::Wire<1> rs1_nodep;
dark::Wire<5> rs1_deps;
dark::Wire<1> rs2_nodep;
dark::Wire<5> rs2_deps;
// dark::Wire<1> rs1_nodep;
// dark::Wire<5> rs1_deps;
// dark::Wire<1> rs2_nodep;
// dark::Wire<5> rs2_deps;
};
struct CentralScheduleUnit_Output {
dark::Register<1> force_clear_announcer;
@ -40,6 +40,7 @@ struct CentralScheduleUnit_Output {
dark::Register<5> issue_ROB_index;
dark::Register<7 + 3 + 1> full_ins_id;
dark::Register<32> full_ins;
dark::Register<32> issuing_PC;
dark::Register<5> decoded_rd;
dark::Register<1> has_decoded_rd;
dark::Register<5> decoded_rs1;
@ -55,6 +56,10 @@ struct CentralScheduleUnit_Output {
dark::Register<1> cache_hit;
dark::Register<5> cache_hit_ROB_index;
dark::Register<32> cache_hit_data;
dark::Register<1> is_committing;
dark::Register<5> commit_reg_index;
dark::Register<32> commit_reg_value;
dark::Register<5> commit_ins_ROB_index;
};
struct ROBRecordType {
dark::Register<4> state;
@ -100,6 +105,11 @@ struct CentralScheduleUnit
ROB_tail <= 0;
ROB_remain_space <= kROBSize;
}
// STEP1: try to commit and see if we need to rollback
// process memory access request from LSQ
// listen to the data from Memory and ALU
// try to issue and check if we need to stall
// provide the potentially missing data for instruction issued last cycle
}
};
} // namespace ZYM

62
include/loadstorequeue.h
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@ -1,5 +1,6 @@
#pragma once
#ifndef LOADSTOREQUEUE_H
#include <array>
#include "tools.h"
namespace ZYM {
struct LoadStoreQueue_Input {
@ -9,8 +10,9 @@ struct LoadStoreQueue_Input {
dark::Wire<1> is_issuing;
dark::Wire<1> issue_type;
dark::Wire<5> issue_ROB_index;
dark::Wire<7+3+1> full_ins_id;
dark::Wire<7 + 3 + 1> full_ins_id;
dark::Wire<32> full_ins;
dark::Wire<32> issuing_PC;
dark::Wire<5> decoded_rd;
dark::Wire<1> has_decoded_rd;
dark::Wire<5> decoded_rs1;
@ -50,18 +52,64 @@ struct LoadStoreQueue_Output {
dark::Register<32> request_data_output;
dark::Register<6> LSQ_remain_space_output;
};
struct LSQ_Record {
dark::Register<2> state; // 0: no, 1: initializing dependency, 2: waiting for data
dark::Register<7 + 3 + 1> full_ins_id;
dark::Register<32> Vj, Vk;
dark::Register<5> Qj, Qk;
dark::Register<5> ins_ROB_index;
dark::Register<32> ins_self_PC;
dark::Register<32> ins_imm;
dark::Register<32> addr;
};
struct LoadStoreQueue_Private {
dark::Register<5> LSQ_head;
dark::Register<5> LSQ_tail;
dark::Register<6> LSQ_remain_space;
std::array<LSQ_Record, 32> LSQ_queue;
dark::Register<1> has_accepted_ins_last_cycle;
dark::Register<5> last_cycle_ins_LSQ_index;
};
struct LoadStoreQueue: public dark::Module<LoadStoreQueue_Input,LoadStoreQueue_Output,LoadStoreQueue_Private> {
LoadStoreQueue() {
// Constructor
struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue_Output, LoadStoreQueue_Private> {
LoadStoreQueue() {
// Constructor
}
void work() {
if (bool(reset)) {
LSQ_remain_space <= 32;
LSQ_head <= 0;
LSQ_tail <= 0;
for (auto &record : LSQ_queue) {
record.state <= 0;
}
has_accepted_ins_last_cycle <= 0;
return;
}
void work() {
// Update function
if (bool(force_clear_receiver)) {
LSQ_remain_space <= 32;
LSQ_head <= 0;
LSQ_tail <= 0;
for (auto &record : LSQ_queue) {
record.state <= 0;
}
has_accepted_ins_last_cycle <= 0;
return;
}
if (bool(is_issuing) && issue_type == 1) {
#ifdef _DEBUG
if (LSQ_remain_space == 0 || LSQ_remain_space > 32) throw std::runtime_error("LSQ_remain_space is out of range");
#endif
has_accepted_ins_last_cycle <= 1;
// TODO: now we can accept the instruction, that is, to store it in the LSQ
} else
has_accepted_ins_last_cycle <= 0;
if (bool(has_accepted_ins_last_cycle)) {
// TODO: now dependency info can be read from the register file, in the mean time, CSU will provide the
// potentially missing data
}
// TODO: now alu, memory (and L0 cache of memory) may provide data to satisfy the dependency
// TODO: now, we can check if we can execute the instruction, memory and L0 cache will listen to this
}
};
}
} // namespace ZYM
#endif

75
include/registerfile.h
View File

@ -1,7 +1,10 @@
#pragma once
#include "concept.h"
#ifndef REGISTERFILE_H
#include <array>
#include "tools.h"
namespace ZYM {
const static size_t kTotalRegisters = 32;
struct RegisterFile_Input {
// receive control signal from CSU
dark::Wire<1> reset;
@ -9,7 +12,7 @@ struct RegisterFile_Input {
dark::Wire<1> is_issuing;
dark::Wire<1> issue_type;
dark::Wire<5> issue_ROB_index;
dark::Wire<7+3+1> full_ins_id;
dark::Wire<7 + 3 + 1> full_ins_id;
dark::Wire<32> full_ins;
dark::Wire<5> decoded_rd;
dark::Wire<1> has_decoded_rd;
@ -17,6 +20,10 @@ struct RegisterFile_Input {
dark::Wire<1> has_decoded_rs1;
dark::Wire<5> decoded_rs2;
dark::Wire<1> has_decoded_rs2;
dark::Wire<1> is_committing;
dark::Wire<5> commit_ins_ROB_index;
dark::Wire<5> commit_reg_index;
dark::Wire<32> commit_reg_value;
};
struct RegisterFile_Output {
dark::Register<1> rs1_nodep;
@ -26,13 +33,63 @@ struct RegisterFile_Output {
dark::Register<5> rs2_deps;
dark::Register<32> rs2_value;
};
struct RegisterFile : public dark::Module<RegisterFile_Input, RegisterFile_Output> {
RegisterFile() {
// Constructor
}
void work() {
// Update function
}
struct RegisterFile_Private {
std::array<dark::Register<32>, kTotalRegisters> registers;
std::array<dark::Register<5>, kTotalRegisters> register_deps;
std::array<dark::Register<1>, kTotalRegisters> register_nodep;
};
}
struct RegisterFile : public dark::Module<RegisterFile_Input, RegisterFile_Output, RegisterFile_Private> {
RegisterFile() {
// Constructor
}
void work() {
if (bool(reset)) {
for(auto& reg : registers) {
reg <= 0;
}
for(auto& reg : register_deps) {
reg <= 0;
}
for(auto& reg : register_nodep) {
reg <= 1;
}
return;
}
if(bool(is_committing)) {
registers[static_cast<max_size_t>(commit_reg_index)] <= commit_reg_value;
if(register_deps[static_cast<max_size_t>(commit_reg_index)] == commit_ins_ROB_index) {
register_nodep[static_cast<max_size_t>(commit_reg_index)] <= 1;
}
}
if(bool(is_issuing)) {
if(bool(has_decoded_rs1)) {
if((!bool(is_committing))||(commit_reg_index != decoded_rs1)) {
rs1_deps <= register_deps[static_cast<max_size_t>(decoded_rs1)];
rs1_value <= registers[static_cast<max_size_t>(decoded_rs1)];
rs1_nodep <= register_nodep[static_cast<max_size_t>(decoded_rs1)];
} else {
rs1_deps <= 0;
rs1_value <= commit_reg_value;
rs1_nodep <= 1;
}
}
if(bool(has_decoded_rs2)) {
if((!bool(is_committing))||(commit_reg_index != decoded_rs2)) {
rs2_deps <= register_deps[static_cast<max_size_t>(decoded_rs2)];
rs2_value <= registers[static_cast<max_size_t>(decoded_rs2)];
rs2_nodep <= register_nodep[static_cast<max_size_t>(decoded_rs2)];
} else {
rs2_deps <= 0;
rs2_value <= commit_reg_value;
rs2_nodep <= 1;
}
}
if(bool(has_decoded_rd)) {
register_deps[static_cast<max_size_t>(decoded_rd)] <= static_cast<max_size_t>(issue_ROB_index);
register_nodep[static_cast<max_size_t>(decoded_rd)] <= 0;
}
}
}
};
} // namespace ZYM
#endif

64
include/reservestation.h
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@ -1,5 +1,6 @@
#pragma once
#ifndef RESERVATIONSTATION_H
#include <array>
#include "tools.h"
namespace ZYM {
struct ReserveStation_Input {
@ -9,8 +10,9 @@ struct ReserveStation_Input {
dark::Wire<1> is_issuing;
dark::Wire<1> issue_type;
dark::Wire<5> issue_ROB_index;
dark::Wire<7+3+1> full_ins_id;
dark::Wire<7 + 3 + 1> full_ins_id;
dark::Wire<32> full_ins;
dark::Wire<32> issuing_PC;
dark::Wire<5> decoded_rd;
dark::Wire<1> has_decoded_rd;
dark::Wire<5> decoded_rs1;
@ -45,23 +47,67 @@ struct ReserveStation_Input {
};
struct ReserveStation_Output {
// alu will listen for these:
dark::Register<7+3+1> request_full_id;
dark::Register<7 + 3 + 1> request_full_id;
dark::Register<32> operand1;
dark::Register<32> operand2;
dark::Register<5> request_ROB_index;
dark::Register<6> RS_remain_space_output;
};
struct RS_Record {
dark::Register<2> state; // 0: no, 1: initializing dependency, 2: waiting for data
dark::Register<7 + 3 + 1> full_ins_id;
dark::Register<32> Vj, Vk;
dark::Register<5> Qj, Qk;
dark::Register<5> ins_ROB_index;
dark::Register<32> ins_self_PC;
dark::Register<32> ins_imm;
dark::Register<32> addr;
};
struct ReserveStation_Private {
dark::Register<5> RS_head;
dark::Register<5> RS_tail;
dark::Register<6> RS_remaining_space;
std::array<RS_Record, 32> RS_records;
dark::Register<1> has_accepted_ins_last_cycle;
};
struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation_Output, ReserveStation_Private> {
ReserveStation() {
// Constructor
ReserveStation() {
// Constructor
}
void work() {
// Update function
if (bool(reset)) {
for (auto &record : RS_records) {
record.state <= 0;
}
RS_remaining_space <= 32;
request_full_id <= 0;
return;
}
void work() {
// Update function
if (bool(force_clear_receiver)) {
for (auto &record : RS_records) {
record.state <= 0;
}
RS_remaining_space <= 32;
request_full_id <= 0;
return;
}
if (bool(is_issuing) && issue_type == 0) {
#ifdef _DEBUG
if (RS_remaining_space == 0 || RS_remaining_space > 32) {
std::cerr << "Reserve Station is full, cannot issue new instruction" << std::endl;
return;
}
#endif
has_accepted_ins_last_cycle <= 1;
// TODO: to something to accept the instruction
} else
has_accepted_ins_last_cycle <= 0;
if (bool(has_accepted_ins_last_cycle)) {
// TODO: now dependency info can be read from the register file, in the mean time, CSU will provide the
// potentially missing data
}
// TODO: now alu, memory (and L0 cache of memory) may provide data to satisfy the dependency
// TODO: now, we can check if we can execute the instruction, memory and L0 cache will listen to this
}
};
}
} // namespace ZYM
#endif