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# RISC-V Simulator Template
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A template which enables you to write verilog-like C++ code.
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## How to use
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### Include the library
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This is a header-only library, which means you just need to include all your required headers in your project.
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We strongly recommend you to include `include/tools` to simply include all the headers.
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```cpp
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#include "include/tools.h"
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```
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### Debug mode
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We provide a debug mode, which will perform more checks in the code. To enable that,
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just define the macro `_DEBUG` before including the headers.
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You may also pass `-D _DEBUG` to the compiling command to define the macro.
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```cpp
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#define _DEBUG
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```
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### Components
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You may at first treat all these components as the verilog integers.
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You may assume all the types below support basic arithmetic operations,
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and will clip the value just as the verilog integers operations.
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#### Register
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Registers are just like the registers in the verilog.
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To simulate the registers, a `Register` is only allowed to be assigned once in a cycle.
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```cpp
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// Declare a 32-bit register
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// The maximum bit-width depends on the max_size_t
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// Currently, the max_size_t is std::uint32_t
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Register<32> reg;
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reg <= reg + 1; // OK, allow to assign from some value with the same bit-width
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Register<16> reg2;
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reg <= reg2 * reg2; // Compile error, the bit-width is different (32 vs 16)
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```
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#### Wire
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Wires are also similar to the wires in the verilog.
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It should be assigned exactly once before reading.
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It can accept a function-like input (function pointers/lambdas) to extract the value.
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```cpp
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// Declare a 4-bit wire
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Wire<4> wire;
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Register<4> reg;
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// OK, assign the value from an integer
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// Be careful, the value may be clipped
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wire = []() { return 0b11010; }; // Clipped to 0b1010
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// OK, assign the value from a register
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// When the register's value changes,
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// the wire's value will also change
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Wire <4> wire2 = [®]() -> auto & { return reg; };
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// Ill formed! The wire is assigned twice
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wire = []() { return 0b11010; };
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// Ill formed! Wire can not accept a value
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// with different bit-width
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Wire <5> wire3 = [&]() -> auto & { return reg + 4; };
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```
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#### Bit
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Bit is an intermediate type, which can be used to represent an integer with some bit_width.
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```cpp
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Bit <5> b = 0b111111; // Clipped to 0b11111
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b.set <4, 2> (0b110); // Set bit 4, 3, 2 to 1, 1, 0
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b.set <4> (0); // Set bit 4 to 0
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Bit <3> c = b.range <3, 1>; // Copy bit 3, 2, 1 to c
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Bit <4> d = b.slice <4> (1); // Copy 4 bits from bit 1 (bit 4, 3, 2, 1) to d
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Bit <1> e = d[0]; // Get the 0-th bit of d
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Bit f = { b + 3, c, d }; // Concatenate b + 3, c, d from high to low
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```
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## Deficiencies
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- We do not support Combination Circuit directly now. You may simulate that by simpling using normal integers as intermediate values, and arrange a good order to update the values.
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- We have not implement all the operators on those `integer-like` types. This will be done in the near future.
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- We do no support `signed` types now.
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## TODO
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