finish design, ready to write
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@ -1,16 +1,20 @@
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#pragma once
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#include "module.h"
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#include "wire.h"
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#include <algorithm>
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#include <memory>
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#include <random>
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#include <vector>
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namespace dark {
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class CPU {
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private:
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std::vector<std::unique_ptr<ModuleBase>> mod_owned;
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std::vector<ModuleBase *> modules;
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bool reset_signal = false;
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dark::Wire<1> halt_signal;
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public:
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unsigned long long cycles = 0;
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@ -53,10 +57,16 @@ public:
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module->work();
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sync_all();
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}
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bool GetResetSignal(){
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return reset_signal;
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}
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void run(unsigned long long max_cycles = 0, bool shuffle = false) {
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auto func = shuffle ? &CPU::run_once_shuffle : &CPU::run_once;
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while (max_cycles == 0 || cycles < max_cycles)
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reset_signal=true;
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while (max_cycles == 0 || cycles < max_cycles) {
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(this->*func)();
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reset_signal=false;
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}
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}
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};
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