ready to fulfill detail functions
This commit is contained in:
@ -1,6 +1,7 @@
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#pragma once
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#ifndef ALU_H
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#include "tools.h"
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namespace ZYM {
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struct ALU_Input {
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dark::Wire<7 + 3 + 1> request_full_id;
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dark::Wire<32> operand1;
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@ -8,16 +9,18 @@ struct ALU_Input {
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dark::Wire<5> request_ROB_index;
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};
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struct ALU_Output {
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dark::Register<1> done;
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dark::Register<32> result;
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dark::Register<2> alu_status;
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dark::Register<5> result_ROB_index;
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dark::Register<32> result;
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dark::Register<32> completed_alu_resulting_PC;
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};
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struct ALU : public dark::Module<ALU_Input, ALU_Output> {
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ALU() {
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// Constructor
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}
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void update() {
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void work() {
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// Update function
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}
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};
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}
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#endif
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@ -16,6 +16,11 @@ struct CentralScheduleUnit_Input {
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dark::Wire<2> mem_status_receiver;
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dark::Wire<5> completed_memins_ROB_index;
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dark::Wire<32> completed_memins_read_data;
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// data from LoadStoreQueue
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dark::Wire<4> mem_request_type_input;
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dark::Wire<32> mem_address_input;
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dark::Wire<32> mem_data_input;
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dark::Wire<5> mem_request_ROB_index;
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// data from alu
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dark::Wire<2> alu_status_receiver;
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dark::Wire<5> completed_aluins_ROB_index;
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@ -39,10 +44,17 @@ struct CentralScheduleUnit_Output {
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dark::Register<1> has_decoded_rd;
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dark::Register<5> decoded_rs1;
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dark::Register<1> has_decoded_rs1;
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dark::Register<1> rs1_is_in_ROB;
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dark::Register<32> rs1_in_ROB_value;
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dark::Register<5> decoded_rs2;
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dark::Register<1> has_decoded_rs2;
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dark::Register<1> rs2_is_in_ROB;
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dark::Register<32> rs2_in_ROB_value;
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dark::Register<32> decoded_imm;
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dark::Register<6> decoded_shamt;
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dark::Register<1> cache_hit;
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dark::Register<5> cache_hit_ROB_index;
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dark::Register<32> cache_hit_data;
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};
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struct ROBRecordType {
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dark::Register<4> state;
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@ -1,6 +1,7 @@
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#pragma once
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#ifndef LOADSTOREQUEUE_H
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#include "tools.h"
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namespace ZYM {
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struct LoadStoreQueue_Input {
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// receive control signal from CSU
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dark::Wire<1> reset;
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@ -14,9 +15,24 @@ struct LoadStoreQueue_Input {
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dark::Wire<1> has_decoded_rd;
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dark::Wire<5> decoded_rs1;
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dark::Wire<1> has_decoded_rs1;
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dark::Wire<1> rs1_is_in_ROB;
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dark::Wire<32> rs1_in_ROB_value;
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dark::Wire<5> decoded_rs2;
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dark::Wire<1> has_decoded_rs2;
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dark::Wire<1> rs2_is_in_ROB;
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dark::Wire<32> rs2_in_ROB_value;
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dark::Wire<32> decoded_imm;
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// receive data from register file
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dark::Wire<1> rs1_nodep;
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dark::Wire<5> rs1_deps;
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dark::Wire<32> rs1_value;
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dark::Wire<1> rs2_nodep;
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dark::Wire<5> rs2_deps;
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dark::Wire<32> rs2_value;
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// data from alu
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dark::Wire<2> alu_status_receiver;
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dark::Wire<5> completed_aluins_ROB_index;
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dark::Wire<32> completed_aluins_result;
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// receive status signal from Memory
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dark::Wire<2> mem_data_sign;
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dark::Wire<5> completed_memins_ROB_index;
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@ -32,6 +48,7 @@ struct LoadStoreQueue_Output {
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dark::Register<5> request_ROB_index;
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dark::Register<32> request_address_output;
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dark::Register<32> request_data_output;
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dark::Register<6> LSQ_remain_space_output;
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};
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struct LoadStoreQueue_Private {
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dark::Register<5> LSQ_head;
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@ -42,8 +59,9 @@ struct LoadStoreQueue: public dark::Module<LoadStoreQueue_Input,LoadStoreQueue_O
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LoadStoreQueue() {
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// Constructor
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}
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void update() {
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void work() {
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// Update function
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}
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};
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}
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#endif
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@ -1,6 +1,7 @@
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#pragma once
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#ifndef REGISTERFILE_H
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#include "tools.h"
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namespace ZYM {
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struct RegisterFile_Input {
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// receive control signal from CSU
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dark::Wire<1> reset;
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@ -29,8 +30,9 @@ struct RegisterFile : public dark::Module<RegisterFile_Input, RegisterFile_Outpu
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RegisterFile() {
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// Constructor
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}
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void update() {
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void work() {
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// Update function
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}
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};
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}
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#endif
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@ -1,6 +1,7 @@
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#pragma once
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#ifndef RESERVATIONSTATION_H
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#include "tools.h"
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namespace ZYM {
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struct ReserveStation_Input {
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// receive control signal from CSU
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dark::Wire<1> reset;
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@ -14,8 +15,12 @@ struct ReserveStation_Input {
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dark::Wire<1> has_decoded_rd;
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dark::Wire<5> decoded_rs1;
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dark::Wire<1> has_decoded_rs1;
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dark::Wire<1> rs1_is_in_ROB;
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dark::Wire<32> rs1_in_ROB_value;
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dark::Wire<5> decoded_rs2;
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dark::Wire<1> has_decoded_rs2;
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dark::Wire<1> rs2_is_in_ROB;
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dark::Wire<32> rs2_in_ROB_value;
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dark::Wire<32> decoded_imm;
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dark::Wire<6> decoded_shamt;
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// receive data from register file
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@ -25,6 +30,18 @@ struct ReserveStation_Input {
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dark::Wire<1> rs2_nodep;
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dark::Wire<5> rs2_deps;
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dark::Wire<32> rs2_value;
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// data from alu
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dark::Wire<2> alu_status_receiver;
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dark::Wire<5> completed_aluins_ROB_index;
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dark::Wire<32> completed_aluins_result;
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// data from Memory
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dark::Wire<2> mem_status_receiver;
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dark::Wire<5> completed_memins_ROB_index;
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dark::Wire<32> completed_memins_read_data;
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// receive status signal from L0 cache(data from Memory)
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dark::Wire<1> cache_hit;
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dark::Wire<5> cache_hit_ROB_index;
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dark::Wire<32> cache_hit_data;
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};
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struct ReserveStation_Output {
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// alu will listen for these:
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@ -32,6 +49,7 @@ struct ReserveStation_Output {
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dark::Register<32> operand1;
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dark::Register<32> operand2;
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dark::Register<5> request_ROB_index;
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dark::Register<6> RS_remain_space_output;
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};
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struct ReserveStation_Private {
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dark::Register<5> RS_head;
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@ -41,8 +59,9 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
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ReserveStation() {
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// Constructor
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}
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void update() {
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void work() {
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// Update function
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}
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};
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}
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#endif
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142
src/main.cpp
142
src/main.cpp
@ -6,20 +6,154 @@
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#include "registerfile.h"
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#include "reservestation.h"
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#include "tools.h"
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template <int N>
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inline static void DirectWireConnect(dark::Register<N> &src, dark::Wire<N> &dest) {
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template <std::size_t N>
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inline static void RWConnect(dark::Register<N> &src, dark::Wire<N> &dest) {
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dest.assign([&]() -> auto & { return src; });
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}
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int main(int argc, char **argv) {
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dark::CPU cpu;
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ZYM::CentralScheduleUnit csu;
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ZYM::Memory memory;
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ZYM::LoadStoreQueue lsq;
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ZYM::ALU alu;
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ZYM::RegisterFile rf;
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ZYM::ReserveStation rs;
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cpu.add_module(&csu);
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cpu.add_module(&memory);
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cpu.add_module(&lsq);
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cpu.add_module(&alu);
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cpu.add_module(&rf);
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cpu.add_module(&rs);
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// some basic siganls
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cpu.halt_signal.assign([&]() -> auto & { return csu.halt_signal; });
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memory.reset = [&]() { return cpu.GetResetSignal(); };
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memory.LoadProgram(std::cin);
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csu.SetInstructionFetcher([&](auto addr) { return memory.FetchInstruction(addr); });
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csu.reset.assign([&]() { return cpu.GetResetSignal(); });
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memory.reset.assign([&]() { return cpu.GetResetSignal(); });
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memory.LoadProgram(std::cin);
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lsq.reset.assign([&]() { return cpu.GetResetSignal(); });
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// alu.reset.assign([&]() { return cpu.GetResetSignal(); });
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rf.reset.assign([&]() { return cpu.GetResetSignal(); });
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rs.reset.assign([&]() { return cpu.GetResetSignal(); });
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// now connect the wires, see the comment and docs for help
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// csu <-> memory
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RWConnect(csu.force_clear_announcer, memory.force_clear_receiver);
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RWConnect(memory.data_sign, csu.mem_status_receiver);
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RWConnect(memory.completed_memins_ROB_index, csu.completed_memins_ROB_index);
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RWConnect(memory.completed_memins_read_data, csu.completed_memins_read_data);
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// csu <-> lsq
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RWConnect(csu.force_clear_announcer, lsq.force_clear_receiver);
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RWConnect(csu.is_issuing, lsq.is_issuing);
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RWConnect(csu.issue_type, lsq.issue_type);
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RWConnect(csu.issue_ROB_index, lsq.issue_ROB_index);
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RWConnect(csu.full_ins_id, lsq.full_ins_id);
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RWConnect(csu.full_ins, lsq.full_ins);
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RWConnect(csu.decoded_rd, lsq.decoded_rd);
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RWConnect(csu.has_decoded_rd, lsq.has_decoded_rd);
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RWConnect(csu.decoded_rs1, lsq.decoded_rs1);
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RWConnect(csu.has_decoded_rs1, lsq.has_decoded_rs1);
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RWConnect(csu.rs1_is_in_ROB, lsq.rs1_is_in_ROB);
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RWConnect(csu.rs1_in_ROB_value, lsq.rs1_in_ROB_value);
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RWConnect(csu.decoded_rs2, lsq.decoded_rs2);
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RWConnect(csu.has_decoded_rs2, lsq.has_decoded_rs2);
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RWConnect(csu.rs2_is_in_ROB, lsq.rs2_is_in_ROB);
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RWConnect(csu.rs2_in_ROB_value, lsq.rs2_in_ROB_value);
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RWConnect(csu.decoded_imm, lsq.decoded_imm);
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RWConnect(csu.cache_hit, lsq.cache_hit);
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RWConnect(csu.cache_hit_ROB_index, lsq.cache_hit_ROB_index);
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RWConnect(csu.cache_hit_data, lsq.cache_hit_data);
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RWConnect(lsq.request_type_output, csu.mem_request_type_input);
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RWConnect(lsq.request_ROB_index, csu.mem_request_ROB_index);
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RWConnect(lsq.request_address_output, csu.mem_address_input);
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RWConnect(lsq.request_data_output, csu.mem_data_input);
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RWConnect(lsq.LSQ_remain_space_output, csu.load_store_queue_emptyspace_receiver);
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// csu <-> alu
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RWConnect(alu.alu_status, csu.alu_status_receiver);
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RWConnect(alu.result_ROB_index, csu.completed_aluins_ROB_index);
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RWConnect(alu.result, csu.completed_aluins_result);
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RWConnect(alu.completed_alu_resulting_PC, csu.completed_alu_resulting_PC);
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// csu <-> register file
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RWConnect(csu.force_clear_announcer, rf.force_clear_receiver);
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RWConnect(csu.is_issuing, rf.is_issuing);
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RWConnect(csu.issue_type, rf.issue_type);
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RWConnect(csu.issue_ROB_index, rf.issue_ROB_index);
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RWConnect(csu.full_ins_id, rf.full_ins_id);
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RWConnect(csu.full_ins, rf.full_ins);
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RWConnect(csu.decoded_rd, rf.decoded_rd);
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RWConnect(csu.has_decoded_rd, rf.has_decoded_rd);
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RWConnect(csu.decoded_rs1, rf.decoded_rs1);
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RWConnect(csu.has_decoded_rs1, rf.has_decoded_rs1);
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RWConnect(csu.decoded_rs2, rf.decoded_rs2);
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RWConnect(csu.has_decoded_rs2, rf.has_decoded_rs2);
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RWConnect(rf.rs1_nodep, csu.rs1_nodep);
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RWConnect(rf.rs1_deps, csu.rs1_deps);
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RWConnect(rf.rs2_nodep, csu.rs2_nodep);
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RWConnect(rf.rs2_deps, csu.rs2_deps);
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// csu <-> reserve station
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RWConnect(csu.force_clear_announcer, rs.force_clear_receiver);
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RWConnect(csu.is_issuing, rs.is_issuing);
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RWConnect(csu.issue_type, rs.issue_type);
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RWConnect(csu.issue_ROB_index, rs.issue_ROB_index);
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RWConnect(csu.full_ins_id, rs.full_ins_id);
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RWConnect(csu.full_ins, rs.full_ins);
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RWConnect(csu.decoded_rd, rs.decoded_rd);
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RWConnect(csu.has_decoded_rd, rs.has_decoded_rd);
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RWConnect(csu.decoded_rs1, rs.decoded_rs1);
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RWConnect(csu.has_decoded_rs1, rs.has_decoded_rs1);
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RWConnect(csu.rs1_is_in_ROB, rs.rs1_is_in_ROB);
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RWConnect(csu.rs1_in_ROB_value, rs.rs1_in_ROB_value);
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RWConnect(csu.decoded_rs2, rs.decoded_rs2);
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RWConnect(csu.has_decoded_rs2, rs.has_decoded_rs2);
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RWConnect(csu.rs2_is_in_ROB, rs.rs2_is_in_ROB);
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RWConnect(csu.rs2_in_ROB_value, rs.rs2_in_ROB_value);
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RWConnect(csu.decoded_imm, rs.decoded_imm);
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RWConnect(csu.decoded_shamt, rs.decoded_shamt);
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RWConnect(csu.cache_hit, rs.cache_hit);
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RWConnect(csu.cache_hit_ROB_index, rs.cache_hit_ROB_index);
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RWConnect(csu.cache_hit_data, rs.cache_hit_data);
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RWConnect(rs.RS_remain_space_output, csu.reservestation_emptyspace_receiver);
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// memory <-> lsq
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RWConnect(memory.data_sign, lsq.mem_data_sign);
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RWConnect(memory.completed_memins_ROB_index, lsq.completed_memins_ROB_index);
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RWConnect(memory.completed_memins_read_data, lsq.completed_memins_read_data);
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RWConnect(lsq.request_type_output, memory.request_type_input);
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RWConnect(lsq.request_ROB_index, memory.request_ROB_index);
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RWConnect(lsq.request_address_output, memory.address_input);
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RWConnect(lsq.request_data_output, memory.data_input);
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// memory <-> alu : no connections
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// memory <-> register file : no connections
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// memory <-> reserve station :
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RWConnect(memory.data_sign, rs.mem_status_receiver);
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RWConnect(memory.completed_memins_ROB_index, rs.completed_memins_ROB_index);
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RWConnect(memory.completed_memins_read_data, rs.completed_memins_read_data);
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// lsq <-> alu :
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RWConnect(alu.alu_status, lsq.alu_status_receiver);
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RWConnect(alu.result_ROB_index, lsq.completed_aluins_ROB_index);
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RWConnect(alu.result, lsq.completed_aluins_result);
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// lsq <-> register file
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RWConnect(rf.rs1_nodep, lsq.rs1_nodep);
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RWConnect(rf.rs1_deps, lsq.rs1_deps);
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RWConnect(rf.rs1_value, lsq.rs1_value);
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RWConnect(rf.rs2_nodep, lsq.rs2_nodep);
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RWConnect(rf.rs2_deps, lsq.rs2_deps);
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RWConnect(rf.rs2_value, lsq.rs2_value);
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// lsq <-> reserve station : no connections
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// alu <-> register file : no connections
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// alu <-> reserve station
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RWConnect(rs.request_full_id, alu.request_full_id);
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RWConnect(rs.operand1, alu.operand1);
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RWConnect(rs.operand2, alu.operand2);
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RWConnect(rs.request_ROB_index, alu.request_ROB_index);
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RWConnect(alu.alu_status, rs.alu_status_receiver);
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RWConnect(alu.result_ROB_index, rs.completed_aluins_ROB_index);
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RWConnect(alu.result, rs.completed_aluins_result);
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// register file <-> reserve station
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RWConnect(rf.rs1_nodep, rs.rs1_nodep);
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RWConnect(rf.rs1_deps, rs.rs1_deps);
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RWConnect(rf.rs1_value, rs.rs1_value);
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RWConnect(rf.rs2_nodep, rs.rs2_nodep);
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RWConnect(rf.rs2_deps, rs.rs2_deps);
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RWConnect(rf.rs2_value, rs.rs2_value);
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// now start running
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std::cout << cpu.run(0, true) << std::endl;
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return 0;
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}
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