From fd92d6df4a391bb39a39c10a94b489a5cf3e18f5 Mon Sep 17 00:00:00 2001 From: ZhuangYumin Date: Thu, 1 Aug 2024 23:43:18 +0000 Subject: [PATCH] fix queue access in csu.h --- include/csu.h | 48 ++++++++++++++++++++++++---------------- src/rv32iinterpreter.cpp | 2 +- 2 files changed, 30 insertions(+), 20 deletions(-) diff --git a/include/csu.h b/include/csu.h index e6d870a..296af90 100644 --- a/include/csu.h +++ b/include/csu.h @@ -3,6 +3,7 @@ #include #include #include "concept.h" +#include "debug.h" #ifndef CSU_H #include #include @@ -249,14 +250,14 @@ struct CentralScheduleUnit if (static_cast(record.state) == 3) { ROB_head <= (static_cast(ROB_head) + 1) % kROBSize; DEBUG_CERR << "csu is committing instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase - << static_cast(record.instruction) << std::endl; + << static_cast(record.instruction) << std::endl; is_committing <= 1; has_committed = true; commit_has_resulting_register <= record.has_resulting_register; commit_reg_index <= record.resulting_register_idx; commit_reg_value <= record.resulting_register_value; DEBUG_CERR << "commit_reg_index=" << std::dec << commit_reg_index.peek() << " commit_reg_value=" << std::hex - << std::setw(8) << std::setfill('0') << std::uppercase << commit_reg_value.peek() << std::endl; + << std::setw(8) << std::setfill('0') << std::uppercase << commit_reg_value.peek() << std::endl; commit_ins_ROB_index <= i; actual_PC <= static_cast(record.resulting_PC); if (static_cast(record.PC_mismatch_mark) == 1) { @@ -270,7 +271,7 @@ struct CentralScheduleUnit } if (record.instruction == 0x1B07A503) { DEBUG_CERR << "judgeResult loaded from memory is " << std::dec - << static_cast(record.resulting_register_value) << std::endl; + << static_cast(record.resulting_register_value) << std::endl; } } } @@ -298,10 +299,13 @@ struct CentralScheduleUnit has_predicted_PC <= 1; predicted_PC <= res_PC; DEBUG_CERR << "The jalr instruction is committed, now predicted_PC is " << std::hex << std::setw(8) - << std::setfill('0') << std::uppercase << predicted_PC.peek() << std::endl; + << std::setfill('0') << std::uppercase << predicted_PC.peek() << std::endl; } } record.state <= 3; + DEBUG_CERR << "result collecting for instruct " << std::hex << std::setw(8) << std::setfill('0') + << std::uppercase << static_cast(record.instruction) << " with ROB_index=" << std::dec + << i << std::endl; } } }; @@ -335,10 +339,10 @@ struct CentralScheduleUnit static_cast(has_instruction_issued_last_cycle); if (ROB_next_remain_space > 0 && actual_remain_space > 0) { // can issue - DEBUG_CERR << "csu is issuing mem instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase - << instruction << " full_ins_id= " << std::hex << std::setw(8) << std::setfill('0') - << std::uppercase << full_ins_id << " with ROB_index=" << std::dec - << static_cast(ROB_tail) << std::endl; + DEBUG_CERR << "csu is issuing mem instruct " << std::hex << std::setw(8) << std::setfill('0') + << std::uppercase << instruction << " full_ins_id= " << std::hex << std::setw(8) + << std::setfill('0') << std::uppercase << full_ins_id << " with ROB_index=" << std::dec + << static_cast(ROB_tail) << std::endl; is_issuing <= 1; has_instruction_issued_last_cycle <= 1; uint32_t tail = static_cast(ROB_tail); @@ -375,10 +379,10 @@ struct CentralScheduleUnit static_cast(has_instruction_issued_last_cycle); if (ROB_next_remain_space > 0 && actual_remain_space > 0) { // can issue - DEBUG_CERR << "csu is issuing alu instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase - << instruction << " full_ins_id= " << std::hex << std::setw(8) << std::setfill('0') - << std::uppercase << full_ins_id << " with ROB_index=" << std::dec - << static_cast(ROB_tail) << std::endl; + DEBUG_CERR << "csu is issuing alu instruct " << std::hex << std::setw(8) << std::setfill('0') + << std::uppercase << instruction << " full_ins_id= " << std::hex << std::setw(8) + << std::setfill('0') << std::uppercase << full_ins_id << " with ROB_index=" << std::dec + << static_cast(ROB_tail) << std::endl; is_issuing <= 1; has_instruction_issued_last_cycle <= 1; uint32_t tail = static_cast(ROB_tail); @@ -449,34 +453,40 @@ struct CentralScheduleUnit uint8_t rs2 = static_cast(this->decoded_rs2); uint8_t found_rs2 = 0; uint32_t rs2_v; - for (uint32_t ptr = static_cast(ROB_head); - ptr != static_cast(ROB_tail) && (ptr + 1) % kROBSize != static_cast(ROB_tail); - ptr = (ptr + 1) % kROBSize) { + uint32_t ptr = static_cast(ROB_head); + dark::debug::assert(static_cast(ROB_remain_space) < 32, "ROB is empty"); + do { + DEBUG_CERR << "\tptr=" << std::dec << ptr << std::endl; if (ROB_records[ptr].state.peek() == 3) { + DEBUG_CERR << "\tstatus check passed" << std::endl; if (bool(ROB_records[ptr].has_resulting_register) && static_cast(ROB_records[ptr].resulting_register_idx) == rs1) { rs1_v = ROB_records[ptr].resulting_register_value.peek(); found_rs1 = 1; - DEBUG_CERR << "matching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr << " rs1_v=" << std::hex - << std::setw(8) << std::setfill('0') << rs1_v << std::endl; + DEBUG_CERR << "\tmatching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr + << " rs1_v=" << std::hex << std::setw(8) << std::setfill('0') << rs1_v << std::endl; } if (bool(ROB_records[ptr].has_resulting_register) && static_cast(ROB_records[ptr].resulting_register_idx) == rs2) { rs2_v = ROB_records[ptr].resulting_register_value.peek(); found_rs2 = 1; + DEBUG_CERR << "\tmatching rs2=" << std::dec << int(rs2) << " ptr=" << std::dec << ptr + << " rs2_v=" << std::hex << std::setw(8) << std::setfill('0') << rs2_v << std::endl; } } else { if (bool(ROB_records[ptr].has_resulting_register) && static_cast(ROB_records[ptr].resulting_register_idx) == rs1) { found_rs1 = 0; - DEBUG_CERR << "dematching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr << std::endl; + DEBUG_CERR << "\tdematching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr << std::endl; } if (bool(ROB_records[ptr].has_resulting_register) && static_cast(ROB_records[ptr].resulting_register_idx) == rs2) { found_rs2 = 0; + DEBUG_CERR << "\tdematching rs2=" << std::dec << int(rs2) << " ptr=" << std::dec << ptr << std::endl; } } - } + ptr = (ptr + 1) % kROBSize; + } while (ptr != static_cast(ROB_tail) && (ptr + 1) % kROBSize != static_cast(ROB_tail)); this->rs1_is_in_ROB <= found_rs1; this->rs1_in_ROB_value <= rs1_v; this->rs2_is_in_ROB <= found_rs2; diff --git a/src/rv32iinterpreter.cpp b/src/rv32iinterpreter.cpp index d7eb783..d2e14b5 100644 --- a/src/rv32iinterpreter.cpp +++ b/src/rv32iinterpreter.cpp @@ -192,7 +192,7 @@ class RV32IInterpreter { while (Fetch()) { // uint8_t opcode=IR&127; // std::cout<<"PC: "<