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ZYM/RISC-V-Simulator
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13 Commits 1 Branch 0 Tags
f680da291da7e07f8e27177a631d3b23d068fd77
Commit Graph

13 Commits

Author SHA1 Message Date
DarkSharpness
f680da291d fix(concept): add the missing headers 2024-07-11 22:11:26 +08:00
DarkSharpness
72b0c5bcf0 feat(wire & register): implement these 2 components 2024-07-11 21:53:52 +08:00
DarkSharpness
7ebe48fe09 refactor(bit): change some concept constraints 2024-07-11 21:52:53 +08:00
DarkSharpness
5574542bfe feat(bit): complete operators for operation on bit type 2024-07-11 20:56:06 +08:00
DarkSharpness
1693df2820 refactor: redesign the type system | embrace the new bit_type concept 2024-07-11 20:38:05 +08:00
DarkSharpness
f3d2074a79 feat(bit): add at and subscript [] access for bit class 2024-07-11 18:48:42 +08:00
DarkSharpness
f8bb311fcb fix(sync): do not sync const objects 2024-07-11 18:48:02 +08:00
DarkSharpness
7d7602f6e9 feat(debug): disable debug in non-debug mode 2024-07-11 18:47:17 +08:00
DarkSharpness
d4a9987087 fix(bit): fix the wrong pass-by-value for non-bit types 2024-07-11 00:35:42 +08:00
DarkSharpness
4e43d84480 fix(hardware): disable Register from copy/move construct/assignment 2024-07-11 00:32:27 +08:00
DarkSharpness
5f82fe975c feat(bit): add a demo and add some functions for the bit class 2024-07-09 23:19:36 +08:00
DarkSharpness
39254c4557 feat(bit): complete a bit simulate library 2024-07-09 22:54:00 +08:00
DarkSharpness
68dd99a826 initial commit | complete a draft outline 2024-07-09 21:04:36 +08:00
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