115 lines
3.7 KiB
C++
115 lines
3.7 KiB
C++
#pragma once
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#ifndef LOADSTOREQUEUE_H
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#include <array>
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#include "tools.h"
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namespace ZYM {
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struct LoadStoreQueue_Input {
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// receive control signal from CSU
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dark::Wire<1> reset;
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dark::Wire<1> force_clear_receiver;
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dark::Wire<1> is_issuing;
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dark::Wire<1> issue_type;
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dark::Wire<5> issue_ROB_index;
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dark::Wire<7 + 3 + 1> full_ins_id;
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dark::Wire<32> full_ins;
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dark::Wire<32> issuing_PC;
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dark::Wire<5> decoded_rd;
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dark::Wire<1> has_decoded_rd;
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dark::Wire<5> decoded_rs1;
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dark::Wire<1> has_decoded_rs1;
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dark::Wire<1> rs1_is_in_ROB;
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dark::Wire<32> rs1_in_ROB_value;
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dark::Wire<5> decoded_rs2;
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dark::Wire<1> has_decoded_rs2;
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dark::Wire<1> rs2_is_in_ROB;
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dark::Wire<32> rs2_in_ROB_value;
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dark::Wire<32> decoded_imm;
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// receive data from register file
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dark::Wire<1> rs1_nodep;
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dark::Wire<5> rs1_deps;
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dark::Wire<32> rs1_value;
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dark::Wire<1> rs2_nodep;
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dark::Wire<5> rs2_deps;
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dark::Wire<32> rs2_value;
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// data from alu
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dark::Wire<2> alu_status_receiver;
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dark::Wire<5> completed_aluins_ROB_index;
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dark::Wire<32> completed_aluins_result;
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// receive status signal from Memory
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dark::Wire<2> mem_data_sign;
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dark::Wire<5> completed_memins_ROB_index;
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dark::Wire<32> completed_memins_read_data;
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// receive status signal from L0 cache
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dark::Wire<1> cache_hit;
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dark::Wire<5> cache_hit_ROB_index;
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dark::Wire<32> cache_hit_data;
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};
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struct LoadStoreQueue_Output {
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// request signal, Memory and the L0 cache in ROB will listen to this
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dark::Register<4> request_type_output;
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dark::Register<5> request_ROB_index;
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dark::Register<32> request_address_output;
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dark::Register<32> request_data_output;
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dark::Register<6> LSQ_remain_space_output;
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};
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struct LSQ_Record {
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dark::Register<2> state; // 0: no, 1: initializing dependency, 2: waiting for data
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dark::Register<7 + 3 + 1> full_ins_id;
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dark::Register<32> Vj, Vk;
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dark::Register<5> Qj, Qk;
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dark::Register<5> ins_ROB_index;
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dark::Register<32> ins_self_PC;
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dark::Register<32> ins_imm;
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dark::Register<32> addr;
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};
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struct LoadStoreQueue_Private {
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dark::Register<5> LSQ_head;
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dark::Register<5> LSQ_tail;
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dark::Register<6> LSQ_remain_space;
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std::array<LSQ_Record, 32> LSQ_queue;
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dark::Register<1> has_accepted_ins_last_cycle;
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dark::Register<5> last_cycle_ins_LSQ_index;
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};
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struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue_Output, LoadStoreQueue_Private> {
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LoadStoreQueue() {
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// Constructor
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}
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void work() {
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if (bool(reset)) {
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LSQ_remain_space <= 32;
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LSQ_head <= 0;
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LSQ_tail <= 0;
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for (auto &record : LSQ_queue) {
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record.state <= 0;
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}
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has_accepted_ins_last_cycle <= 0;
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return;
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}
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if (bool(force_clear_receiver)) {
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LSQ_remain_space <= 32;
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LSQ_head <= 0;
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LSQ_tail <= 0;
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for (auto &record : LSQ_queue) {
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record.state <= 0;
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}
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has_accepted_ins_last_cycle <= 0;
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return;
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}
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if (bool(is_issuing) && issue_type == 1) {
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#ifdef _DEBUG
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if (LSQ_remain_space == 0 || LSQ_remain_space > 32) throw std::runtime_error("LSQ_remain_space is out of range");
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#endif
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has_accepted_ins_last_cycle <= 1;
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// TODO: now we can accept the instruction, that is, to store it in the LSQ
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} else
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has_accepted_ins_last_cycle <= 0;
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if (bool(has_accepted_ins_last_cycle)) {
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// TODO: now dependency info can be read from the register file, in the mean time, CSU will provide the
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// potentially missing data
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}
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// TODO: now alu, memory (and L0 cache of memory) may provide data to satisfy the dependency
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// TODO: now, we can check if we can execute the instruction, memory and L0 cache will listen to this
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}
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};
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} // namespace ZYM
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#endif |