102 lines
2.2 KiB
C++
102 lines
2.2 KiB
C++
#include "tools.h"
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#include <iostream>
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struct RegFile_Input {
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Wire <5> rs1_index; // Read
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Wire <5> rs2_index; // Read
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Wire <5> wb_index; // Writeback
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Wire <1> wb_enable; // Writeback enabled?
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Wire <32> wb_data; // Data to writeback
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};
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struct RegFile_Output {
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Register <32> rs1_data; // Read
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Register <32> rs2_data; // Read
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};
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struct RegFile_Private {
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std::array <Register<32>, 32> regs;
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};
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struct RegFile : dark::Module <RegFile_Input, RegFile_Output, RegFile_Private> {
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void work() override final {
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rs1_data <= regs[to_unsigned(rs1_index)];
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rs2_data <= regs[to_unsigned(rs2_index)];
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if (wb_enable && wb_index != 0) {
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regs[to_unsigned(wb_index)] <= wb_data;
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}
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}
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};
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struct InsDecode_Input {
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Wire <32> rs1_data;
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Wire <32> rs2_data;
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};
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struct InsDecode_Output {
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Register <5> rs1_index;
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Register <5> rs2_index;
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Register <5> wb_index;
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Register <32> wb_data;
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Register <1> wb_enable;
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};
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struct InsDecode : dark::Module <InsDecode_Input, InsDecode_Output> {
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void work() override final {
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char c;
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max_size_t x;
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max_size_t y;
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std::cin >> c >> x >> y;
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if (c == 'r') {
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rs1_index <= x;
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rs2_index <= y;
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wb_index <= 0;
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wb_data <= 0;
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wb_enable <= 0;
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} else {
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rs1_index <= 0;
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rs2_index <= 0;
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wb_index <= x;
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wb_data <= y;
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wb_enable <= 1;
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}
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std::cout << "rs1_data: " << to_unsigned(rs1_data) << std::endl;
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std::cout << "rs2_data: " << to_unsigned(rs2_data) << std::endl;
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}
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};
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signed main() {
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InsDecode ins_decode;
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RegFile reg_file;
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dark::CPU cpu;
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cpu.add_module(&ins_decode);
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cpu.add_module(®_file);
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reg_file.rs1_index = [&]() -> auto & { return ins_decode.rs1_index; };
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reg_file.rs2_index = [&]() -> auto & { return ins_decode.rs2_index; };
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reg_file.wb_index = [&]() -> auto & { return ins_decode.wb_index; };
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reg_file.wb_enable = [&]() -> auto & { return ins_decode.wb_enable; };
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reg_file.wb_data = [&]() -> auto & { return ins_decode.wb_data; };
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ins_decode.rs1_data = [&]() -> auto & { return reg_file.rs1_data; };
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ins_decode.rs2_data = [&]() -> auto & { return reg_file.rs2_data; };
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cpu.run(114514, true);
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// Demo input:
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// w 1 2 (output 0 0)
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// r 1 2 (output 0 0)
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// w 2 3 (output 0 0)
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// r 1 2 (output 2 0)
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// r 1 2 (output 0 0)
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// r 1 2 (output 2 3)
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return 0;
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}
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