218 lines
7.8 KiB
C++
218 lines
7.8 KiB
C++
#pragma once
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#include <sys/types.h>
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#include "concept.h"
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#ifndef CSU_H
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#include <array>
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#include <functional>
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#include <tuple>
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#include "tools.h"
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namespace ZYM {
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const int kROBSize = 32;
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const int kTotalRegister = 32;
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struct CentralScheduleUnit_Input {
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dark::Wire<1> reset;
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// data from load store queue
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dark::Wire<6> load_store_queue_emptyspace_receiver;
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// data from reservation station
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dark::Wire<6> reservestation_emptyspace_receiver;
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// data from Memory
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dark::Wire<2> mem_status_receiver;
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dark::Wire<5> completed_memins_ROB_index;
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dark::Wire<32> completed_memins_read_data;
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// data from LoadStoreQueue
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dark::Wire<4> mem_request_type_input;
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dark::Wire<32> mem_address_input;
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dark::Wire<32> mem_data_input;
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dark::Wire<5> mem_request_ROB_index;
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// data from alu
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dark::Wire<2> alu_status_receiver;
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dark::Wire<5> completed_aluins_ROB_index;
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dark::Wire<32> completed_aluins_result;
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dark::Wire<32> completed_alu_resulting_PC;
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// receive data from register file
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// dark::Wire<1> rs1_nodep;
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// dark::Wire<5> rs1_deps;
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// dark::Wire<1> rs2_nodep;
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// dark::Wire<5> rs2_deps;
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};
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struct CentralScheduleUnit_Output {
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dark::Register<1> force_clear_announcer;
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dark::Register<9> halt_signal; // The highest bit is the marker, and the rest is the exit code
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dark::Register<1> is_issuing;
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dark::Register<1> issue_type; // 0: alu, 1: mem
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dark::Register<5> issue_ROB_index;
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dark::Register<7 + 3 + 1> full_ins_id;
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dark::Register<32> full_ins;
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dark::Register<32> issuing_PC;
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dark::Register<5> decoded_rd;
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dark::Register<1> has_decoded_rd;
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dark::Register<5> decoded_rs1;
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dark::Register<1> has_decoded_rs1;
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dark::Register<1> rs1_is_in_ROB;
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dark::Register<32> rs1_in_ROB_value;
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dark::Register<5> decoded_rs2;
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dark::Register<1> has_decoded_rs2;
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dark::Register<1> rs2_is_in_ROB;
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dark::Register<32> rs2_in_ROB_value;
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dark::Register<32> decoded_imm;
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dark::Register<6> decoded_shamt;
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dark::Register<1> cache_hit;
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dark::Register<5> cache_hit_ROB_index;
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dark::Register<32> cache_hit_data;
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dark::Register<1> is_committing;
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dark::Register<5> commit_reg_index;
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dark::Register<32> commit_reg_value;
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dark::Register<5> commit_ins_ROB_index;
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};
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struct ROBRecordType {
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dark::Register<4> state;
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dark::Register<32> instruction;
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dark::Register<5> resulting_register_idx;
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dark::Register<32> resulting_register_value;
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dark::Register<1> resulting_PC_ready;
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dark::Register<32> resulting_PC;
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dark::Register<4> mem_request_type; // see memory.h
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dark::Register<32> mem_request_addr;
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dark::Register<32> mem_request_data;
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};
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struct CentralScheduleUnit_Private {
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dark::Register<32> predicted_PC;
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dark::Register<1> has_predicted_PC; // jalr may force the CPU to stall
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dark::Register<32> actual_PC;
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std::array<ROBRecordType, kROBSize> ROB_records;
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dark::Register<5> ROB_head;
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dark::Register<5> ROB_tail;
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dark::Register<6> ROB_remain_space;
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dark::Register<1> has_instruction_issued_last_cycle; // to correctly calculate remain space for next cycle in issue a
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// ins this cycle
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};
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struct CentralScheduleUnit
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: public dark::Module<CentralScheduleUnit_Input, CentralScheduleUnit_Output, CentralScheduleUnit_Private> {
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private:
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std::function<max_size_t(max_size_t)> instruction_fetcher;
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bool instruction_fetcher_initialized = false;
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inline uint8_t ReadBit(uint32_t data, int pos) { return (data >> pos) & 1; }
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inline void WriteBit(uint32_t &data, int pos, uint8_t bit) {
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data &= ~(1 << pos);
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data |= bit << pos;
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}
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std::tuple<dark::Bit<7 + 3 + 1>, dark::Bit<5>, dark::Bit<1>, dark::Bit<5>, dark::Bit<1>, dark::Bit<5>, dark::Bit<1>,
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dark::Bit<32>, dark::Bit<6>>
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Decode(max_size_t ins) {
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// Decode the instruction
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dark::Bit<7 + 3 + 1> full_ins_id;
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dark::Bit<5> decoded_rd;
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dark::Bit<1> has_decoded_rd;
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dark::Bit<5> decoded_rs1;
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dark::Bit<1> has_decoded_rs1;
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dark::Bit<5> decoded_rs2;
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dark::Bit<1> has_decoded_rs2;
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dark::Bit<32> decoded_imm;
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dark::Bit<6> decoded_shamt;
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uint8_t opcode = ins & 0x7F;
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if (opcode == 0b0110011) {
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// R-type
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has_decoded_rd = 1;
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has_decoded_rs1 = 1;
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has_decoded_rs2 = 1;
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decoded_rd = ins >> 7 & 0x1F;
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decoded_rs1 = ins >> 15 & 0x1F;
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decoded_rs2 = ins >> 20 & 0x1F;
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uint8_t funct3 = ins >> 12 & 0x7;
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uint8_t funct7 = ins >> 25 & 0x7F;
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full_ins_id = opcode | (funct3 << 7) | (((funct7 >> 5) & 1) << 10);
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} else if (opcode == 0b1100111 || opcode == 0b0000011 || opcode == 0b0010011) {
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// I-type
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has_decoded_rd = 1;
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has_decoded_rs1 = 1;
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has_decoded_rs2 = 0;
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decoded_rd = ins >> 7 & 0x1F;
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decoded_rs1 = ins >> 15 & 0x1F;
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decoded_imm = ins >> 20;
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uint32_t sign_bit = ins >> 31;
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if (sign_bit) {
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decoded_imm = static_cast<uint32_t>(decoded_imm) | 0xFFFFF000;
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}
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uint8_t funct3 = ins >> 12 & 0x7;
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uint8_t funct7 = ins >> 25 & 0x7F;
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full_ins_id = opcode | (funct3 << 7) | (((funct7 >> 5) & 1) << 10);
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decoded_shamt = ins >> 20 & 0x3F;
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} else if (opcode == 0b0100011) {
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// S-type
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has_decoded_rd = 0;
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has_decoded_rs1 = 1;
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has_decoded_rs2 = 1;
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decoded_rs1 = (ins >> 15) & 0x1F;
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decoded_rs2 = (ins >> 20) & 0x1F;
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decoded_imm = ((ins >> 7) & 0x1F) | ((ins >> 25) << 5);
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uint32_t sign_bit = ins >> 31;
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if (sign_bit) {
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decoded_imm = static_cast<uint32_t>(decoded_imm) | 0xFFFFF000;
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}
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uint8_t funct3 = ins >> 12 & 0x7;
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full_ins_id = opcode | (funct3 << 7);
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} else if (opcode == 0b1100011) {
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// B-type
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has_decoded_rd = 0;
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has_decoded_rs1 = 1;
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has_decoded_rs2 = 1;
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decoded_rs1 = (ins >> 15) & 0x1F;
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decoded_rs2 = (ins >> 20) & 0x1F;
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decoded_imm = (((ins >> 8) & 0xF) << 1) | (((ins >> 25) & 0x3F) << 5) | (((ins >> 7) & 0x1) << 11) |
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(((ins >> 31) & 0x1) << 12);
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uint32_t sign_bit = ins >> 31;
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if (sign_bit) {
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decoded_imm = static_cast<uint32_t>(decoded_imm) | 0xFFFFE000;
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}
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uint8_t funct3 = ins >> 12 & 0x7;
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full_ins_id = opcode | (funct3 << 7);
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} else if(opcode==0b0110111) {
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// U-type
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has_decoded_rd = 1;
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has_decoded_rs1 = 0;
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has_decoded_rs2 = 0;
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decoded_rd = ins >> 7 & 0x1F;
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decoded_imm = ins >> 12;
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full_ins_id = opcode;
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} else if(opcode==0b1101111) {
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// J-type
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has_decoded_rd = 1;
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has_decoded_rs1 = 0;
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has_decoded_rs2 = 0;
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decoded_rd = ins >> 7 & 0x1F;
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decoded_imm = (ins & 0xFF000) | (((ins >> 20) & 1)<<11) | (((ins >> 21) & 0x3FF)<<1) | ((ins >> 31) << 20);
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uint32_t sign_bit = ins >> 31;
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if (sign_bit) {
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decoded_imm = static_cast<uint32_t>(decoded_imm) | 0xFFE00000;
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}
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full_ins_id = opcode;
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} else throw std::runtime_error("Unknown instruction in Decode");
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return std::make_tuple(full_ins_id, decoded_rd, has_decoded_rd, decoded_rs1, has_decoded_rs1, decoded_rs2,
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has_decoded_rs2, decoded_imm, decoded_shamt);
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}
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public:
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CentralScheduleUnit() { ; }
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void SetInstructionFetcher(std::function<max_size_t(max_size_t)> fetcher) {
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if (instruction_fetcher_initialized) throw std::runtime_error("Instruction fetcher has been initialized");
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instruction_fetcher = fetcher;
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instruction_fetcher_initialized = true;
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}
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void work() override final {
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if (bool(reset)) {
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predicted_PC <= 0;
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actual_PC <= 0;
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has_predicted_PC <= 1;
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ROB_head <= 0;
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ROB_tail <= 0;
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ROB_remain_space <= kROBSize;
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}
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// STEP1: try to commit and see if we need to rollback
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// process memory access request from LSQ
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// listen to the data from Memory and ALU
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// try to issue and check if we need to stall
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// provide the potentially missing data for instruction issued last cycle
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}
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};
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} // namespace ZYM
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#endif |