ZYM/RISC-V-Simulator
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adjust output

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This commit is contained in:
ZhuangYumin
2024-08-01 14:20:54 +00:00
parent 90033d5c63
commit 00fc4c945e
10 changed files with 99 additions and 96 deletions
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4
CMakeLists.txt
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@ -1,6 +1,8 @@
cmake_minimum_required(VERSION 3.20)
project(simulator)
if(NOT CMAKE_BUILD_TYPE)
set(CMAKE_BUILD_TYPE "Release" CACHE STRING "Choose the type of build." FORCE)
endif()
file(GLOB_RECURSE sources "src/*.cpp")
set(CMAKE_CXX_STANDARD 20)

10
include/alu.h
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@ -23,7 +23,7 @@ struct ALU : public dark::Module<ALU_Input, ALU_Output> {
// Constructor
}
void work() {
std::cerr << "ALU: cur request_full_id=" << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
DEBUG_CERR << "ALU: cur request_full_id=" << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
<< static_cast<max_size_t>(request_full_id) << " request_ROB_index=" << std::dec
<< static_cast<max_size_t>(request_ROB_index) << std::endl;
switch (static_cast<max_size_t>(request_full_id)) {
@ -42,7 +42,7 @@ struct ALU : public dark::Module<ALU_Input, ALU_Output> {
alu_status <= 0b10;
result_ROB_index <= request_ROB_index;
result <= imm;
std::cerr << "lui: imm=" << std::hex << static_cast<max_size_t>(imm) << std::endl;
DEBUG_CERR << "lui: imm=" << std::hex << static_cast<max_size_t>(imm) << std::endl;
completed_alu_resulting_PC <= static_cast<max_size_t>(request_PC) + 4;
return;
}
@ -67,8 +67,8 @@ struct ALU : public dark::Module<ALU_Input, ALU_Output> {
alu_status <= 0b10;
result_ROB_index <= request_ROB_index;
result <= static_cast<max_size_t>(request_PC) + 4;
std::cerr << "alu: jalr: imm=" << std::hex << static_cast<max_size_t>(imm) << std::endl;
std::cerr << "alu: jalr: operand1=" << std::hex << static_cast<max_size_t>(operand1) << std::endl;
DEBUG_CERR << "alu: jalr: imm=" << std::hex << static_cast<max_size_t>(imm) << std::endl;
DEBUG_CERR << "alu: jalr: operand1=" << std::hex << static_cast<max_size_t>(operand1) << std::endl;
completed_alu_resulting_PC <= ((static_cast<max_size_t>(operand1) + static_cast<max_size_t>(imm)) & 0xfffffffe);
return;
}
@ -145,7 +145,7 @@ struct ALU : public dark::Module<ALU_Input, ALU_Output> {
alu_status <= 0b10;
result_ROB_index <= request_ROB_index;
result <= static_cast<max_size_t>(operand1) + imm;
std::cerr << "\taddi: operand1=" << std::hex << static_cast<max_size_t>(operand1) << " imm=" << std::hex
DEBUG_CERR << "\taddi: operand1=" << std::hex << static_cast<max_size_t>(operand1) << " imm=" << std::hex
<< static_cast<max_size_t>(imm) << " result=" << std::hex << result.peek() << std::endl;
completed_alu_resulting_PC <= static_cast<max_size_t>(request_PC) + 4;
return;

4
include/cpu.h
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@ -65,12 +65,12 @@ public:
auto func = shuffle ? &CPU::run_once_shuffle : &CPU::run_once;
reset_signal=true;
while (max_cycles == 0 || cycles < max_cycles) {
std::cerr<<"\nclock: "<<std::dec<<global_clock<<std::endl;
DEBUG_CERR<<"\nclock: "<<std::dec<<global_clock<<std::endl;
(this->*func)();
reset_signal=false;
halt_signal.sync();
uint32_t halt_signal_value = static_cast<max_size_t>(halt_signal);
std::cerr<<"simulator received halt_signal_value="<<std::dec<<halt_signal_value<<std::endl;
DEBUG_CERR<<"simulator received halt_signal_value="<<std::dec<<halt_signal_value<<std::endl;
if(halt_signal_value &(1<<8)) {
return halt_signal_value&0xff;
}

28
include/csu.h
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@ -248,28 +248,28 @@ struct CentralScheduleUnit
auto &record = ROB_records[i];
if (static_cast<max_size_t>(record.state) == 3) {
ROB_head <= (static_cast<max_size_t>(ROB_head) + 1) % kROBSize;
std::cerr << "csu is committing instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
DEBUG_CERR << "csu is committing instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
<< static_cast<max_size_t>(record.instruction) << std::endl;
is_committing <= 1;
has_committed = true;
commit_has_resulting_register <= record.has_resulting_register;
commit_reg_index <= record.resulting_register_idx;
commit_reg_value <= record.resulting_register_value;
std::cerr << "commit_reg_index=" << std::dec << commit_reg_index.peek() << " commit_reg_value=" << std::hex
DEBUG_CERR << "commit_reg_index=" << std::dec << commit_reg_index.peek() << " commit_reg_value=" << std::hex
<< std::setw(8) << std::setfill('0') << std::uppercase << commit_reg_value.peek() << std::endl;
commit_ins_ROB_index <= i;
actual_PC <= static_cast<max_size_t>(record.resulting_PC);
if (static_cast<max_size_t>(record.PC_mismatch_mark) == 1) {
force_clear_announcer <= 1;
std::cerr << "[warning] csu is announcing rolling back due to PC mismatch" << std::endl;
DEBUG_CERR << "[warning] csu is announcing rolling back due to PC mismatch" << std::endl;
}
ROB_next_remain_space++;
if (record.instruction == 0x0ff00513) {
halt_signal <= (0b100000000 | static_cast<max_size_t>(a0));
std::cerr << "halting with code " << std::dec << int(halt_signal.peek()) << std::endl;
DEBUG_CERR << "halting with code " << std::dec << int(halt_signal.peek()) << std::endl;
}
if (record.instruction == 0x1B07A503) {
std::cerr << "judgeResult loaded from memory is " << std::dec
DEBUG_CERR << "judgeResult loaded from memory is " << std::dec
<< static_cast<max_size_t>(record.resulting_register_value) << std::endl;
}
}
@ -297,7 +297,7 @@ struct CentralScheduleUnit
if ((static_cast<max_size_t>(record.instruction) & 0x7F) == 0b1100111) {
has_predicted_PC <= 1;
predicted_PC <= res_PC;
std::cerr << "The jalr instruction is committed, now predicted_PC is " << std::hex << std::setw(8)
DEBUG_CERR << "The jalr instruction is committed, now predicted_PC is " << std::hex << std::setw(8)
<< std::setfill('0') << std::uppercase << predicted_PC.peek() << std::endl;
}
}
@ -305,12 +305,12 @@ struct CentralScheduleUnit
}
}
};
std::cerr << "csu is listening data from memory" << std::endl;
DEBUG_CERR << "csu is listening data from memory" << std::endl;
if (static_cast<max_size_t>(mem_status_receiver) == 0b10) {
process_data(static_cast<max_size_t>(completed_memins_ROB_index),
static_cast<max_size_t>(completed_memins_read_data), 0);
}
std::cerr << "csu is listening data from alu" << std::endl;
DEBUG_CERR << "csu is listening data from alu" << std::endl;
if (static_cast<max_size_t>(alu_status_receiver) == 0b10) {
process_data(static_cast<max_size_t>(completed_aluins_ROB_index),
static_cast<max_size_t>(completed_aluins_result),
@ -335,7 +335,7 @@ struct CentralScheduleUnit
static_cast<max_size_t>(has_instruction_issued_last_cycle);
if (ROB_next_remain_space > 0 && actual_remain_space > 0) {
// can issue
std::cerr << "csu is issuing mem instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
DEBUG_CERR << "csu is issuing mem instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
<< instruction << " full_ins_id= " << std::hex << std::setw(8) << std::setfill('0')
<< std::uppercase << full_ins_id << " with ROB_index=" << std::dec
<< static_cast<max_size_t>(ROB_tail) << std::endl;
@ -375,7 +375,7 @@ struct CentralScheduleUnit
static_cast<max_size_t>(has_instruction_issued_last_cycle);
if (ROB_next_remain_space > 0 && actual_remain_space > 0) {
// can issue
std::cerr << "csu is issuing alu instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
DEBUG_CERR << "csu is issuing alu instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
<< instruction << " full_ins_id= " << std::hex << std::setw(8) << std::setfill('0')
<< std::uppercase << full_ins_id << " with ROB_index=" << std::dec
<< static_cast<max_size_t>(ROB_tail) << std::endl;
@ -398,7 +398,7 @@ struct CentralScheduleUnit
break;
case 0b1100111:
// jalr
std::cerr << "encounter jalr" << std::endl;
DEBUG_CERR << "encounter jalr" << std::endl;
ROB_records[tail].resulting_PC_ready <= 0;
has_predicted_PC <= 0;
break;
@ -442,7 +442,7 @@ struct CentralScheduleUnit
}
// provide the potentially missing data for instruction issued last cycle
if (bool(has_instruction_issued_last_cycle)) {
std::cerr << "CSU is processing potentially missing data for instruction issued last cycle" << std::endl;
DEBUG_CERR << "CSU is processing potentially missing data for instruction issued last cycle" << std::endl;
uint8_t rs1 = static_cast<max_size_t>(this->decoded_rs1);
uint8_t found_rs1 = 0;
uint32_t rs1_v;
@ -457,7 +457,7 @@ struct CentralScheduleUnit
static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs1) {
rs1_v = ROB_records[ptr].resulting_register_value.peek();
found_rs1 = 1;
std::cerr << "matching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr << " rs1_v=" << std::hex
DEBUG_CERR << "matching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr << " rs1_v=" << std::hex
<< std::setw(8) << std::setfill('0') << rs1_v << std::endl;
}
if (bool(ROB_records[ptr].has_resulting_register) &&
@ -469,7 +469,7 @@ struct CentralScheduleUnit
if (bool(ROB_records[ptr].has_resulting_register) &&
static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs1) {
found_rs1 = 0;
std::cerr << "dematching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr << std::endl;
DEBUG_CERR << "dematching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr << std::endl;
}
if (bool(ROB_records[ptr].has_resulting_register) &&
static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs2) {

70
include/loadstorequeue.h
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@ -125,17 +125,17 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
LSQ_queue[cur_queue_tail].E2 <= has_decoded_rs2;
LSQ_queue[cur_queue_tail].D1 <= 1; // temporarily
LSQ_queue[cur_queue_tail].D2 <= 1; // temporarily
std::cerr << "LoadStoreQueue is accepting instruction" << std::endl;
std::cerr << "\tfull_ins_id: " << std::hex << static_cast<max_size_t>(full_ins_id) << std::endl;
std::cerr << "\tins_ROB_index: " << std::dec << static_cast<max_size_t>(issue_ROB_index) << std::endl;
std::cerr << "\tins_self_PC: " << std::hex << std::setw(8) << std::setfill('0')
DEBUG_CERR << "LoadStoreQueue is accepting instruction" << std::endl;
DEBUG_CERR << "\tfull_ins_id: " << std::hex << static_cast<max_size_t>(full_ins_id) << std::endl;
DEBUG_CERR << "\tins_ROB_index: " << std::dec << static_cast<max_size_t>(issue_ROB_index) << std::endl;
DEBUG_CERR << "\tins_self_PC: " << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(issuing_PC) << std::endl;
std::cerr << "\tins_imm: " << std::hex << static_cast<max_size_t>(decoded_imm) << std::endl;
std::cerr << "\thas_decoded_rs1: " << std::hex << std::setw(8) << std::setfill('0')
DEBUG_CERR << "\tins_imm: " << std::hex << static_cast<max_size_t>(decoded_imm) << std::endl;
DEBUG_CERR << "\thas_decoded_rs1: " << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(has_decoded_rs1) << std::endl;
std::cerr << "\thas_decoded_rs2: " << std::hex << std::setw(8) << std::setfill('0')
DEBUG_CERR << "\thas_decoded_rs2: " << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(has_decoded_rs2) << std::endl;
std::cerr << "\tstored in positon " << std::dec << static_cast<max_size_t>(cur_queue_tail) << " of LSQ"
DEBUG_CERR << "\tstored in positon " << std::dec << static_cast<max_size_t>(cur_queue_tail) << " of LSQ"
<< std::endl;
// LSQ_queue[cur_queue_tail].Q1 <= decoded_rs1; // temporarily, no use
// LSQ_queue[cur_queue_tail].Q2 <= decoded_rs2; // temporarily, no use
@ -147,36 +147,36 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
if (bool(has_accepted_ins_last_cycle)) {
// now dependency info can be read from the register file, in the mean time, CSU will provide the
// potentially missing data
std::cerr << "LoadStoreQueue is process dependency information from register file and ROB" << std::endl;
DEBUG_CERR << "LoadStoreQueue is process dependency information from register file and ROB" << std::endl;
if (bool(LSQ_queue[last_idx].E1) && bool(rs1_nodep)) {
LSQ_queue[last_idx].V1 <= rs1_value;
LSQ_queue[last_idx].D1 <= 1;
last_cycle_V1_proccessed = true;
std::cerr << "\t from register file: LSQ_queue[last_idx].V1=" << std::hex << std::setw(8) << std::setfill('0')
DEBUG_CERR << "\t from register file: LSQ_queue[last_idx].V1=" << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(LSQ_queue[last_idx].V1) << std::endl;
}
if (bool(LSQ_queue[last_idx].E2) && bool(rs2_nodep)) {
LSQ_queue[last_idx].V2 <= rs2_value;
LSQ_queue[last_idx].D2 <= 1;
last_cycle_V2_proccessed = true;
std::cerr << "from register file: LSQ_queue[last_idx].V2=" << std::hex << std::setw(8) << std::setfill('0')
DEBUG_CERR << "from register file: LSQ_queue[last_idx].V2=" << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(LSQ_queue[last_idx].V2) << std::endl;
}
if (bool(LSQ_queue[last_idx].E1) && (!bool(rs1_nodep)) && bool(rs1_is_in_ROB)) {
LSQ_queue[last_idx].V1 <= rs1_in_ROB_value;
LSQ_queue[last_idx].D1 <= 1;
last_cycle_V1_proccessed = true;
std::cerr << "\t from ROB: LSQ_queue[last_idx].V1=" << std::hex << std::setw(8) << std::setfill('0')
DEBUG_CERR << "\t from ROB: LSQ_queue[last_idx].V1=" << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(LSQ_queue[last_idx].V1) << std::endl;
}
if (bool(LSQ_queue[last_idx].E2) && (!bool(rs2_nodep)) && bool(rs2_is_in_ROB)) {
LSQ_queue[last_idx].V2 <= rs2_in_ROB_value;
LSQ_queue[last_idx].D2 <= 1;
last_cycle_V2_proccessed = true;
std::cerr << "from ROB: LSQ_queue[last_idx].V2=" << std::hex << std::setw(8) << std::setfill('0')
DEBUG_CERR << "from ROB: LSQ_queue[last_idx].V2=" << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(LSQ_queue[last_idx].V2) << std::endl;
}
std::cerr << "End of processing dependency information from register file and ROB" << std::endl;
DEBUG_CERR << "End of processing dependency information from register file and ROB" << std::endl;
}
bool should_monitor_V1 =
bool(has_accepted_ins_last_cycle) && bool(LSQ_queue[last_idx].E1) && !last_cycle_V1_proccessed;
@ -184,15 +184,15 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
bool(has_accepted_ins_last_cycle) && bool(LSQ_queue[last_idx].E2) && !last_cycle_V2_proccessed;
// now alu, memory may provide data to satisfy the dependency
auto process_listend_data = [&](uint32_t res_ROB_index, uint32_t res_value) -> void {
std::cerr << "res_ROB_index=" << std::dec << res_ROB_index << std::endl;
std::cerr << "res_value=" << std::hex << std::setw(8) << std::setfill('0') << res_value << std::endl;
std::cerr << "rs1_deps=" << std::dec << static_cast<max_size_t>(rs1_deps) << std::endl;
std::cerr << "rs2_deps=" << std::dec << static_cast<max_size_t>(rs2_deps) << std::endl;
DEBUG_CERR << "res_ROB_index=" << std::dec << res_ROB_index << std::endl;
DEBUG_CERR << "res_value=" << std::hex << std::setw(8) << std::setfill('0') << res_value << std::endl;
DEBUG_CERR << "rs1_deps=" << std::dec << static_cast<max_size_t>(rs1_deps) << std::endl;
DEBUG_CERR << "rs2_deps=" << std::dec << static_cast<max_size_t>(rs2_deps) << std::endl;
uint32_t ptr = static_cast<max_size_t>(LSQ_head);
while (ptr != static_cast<max_size_t>(LSQ_tail)) {
std::cerr << "\tptr=" << std::dec << ptr << std::endl;
DEBUG_CERR << "\tptr=" << std::dec << ptr << std::endl;
if ((!bool(has_accepted_ins_last_cycle)) || ptr != last_idx) {
std::cerr << "\tnormal" << std::endl;
DEBUG_CERR << "\tnormal" << std::endl;
dark::debug::assert(LSQ_queue[ptr].state == 2, "LSQ_queue[ptr].state != 2");
if ((!bool(LSQ_queue[ptr].D1)) && static_cast<max_size_t>(LSQ_queue[ptr].Q1) == res_ROB_index) {
LSQ_queue[ptr].V1 <= res_value;
@ -203,17 +203,17 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
LSQ_queue[ptr].D2 <= 1;
}
} else {
std::cerr << "\timmediately listend data" << std::endl;
std::cerr << "should_monitor_V1=" << should_monitor_V1 << std::endl;
std::cerr << "should_monitor_V2=" << should_monitor_V2 << std::endl;
DEBUG_CERR << "\timmediately listend data" << std::endl;
DEBUG_CERR << "should_monitor_V1=" << should_monitor_V1 << std::endl;
DEBUG_CERR << "should_monitor_V2=" << should_monitor_V2 << std::endl;
if (should_monitor_V1 && static_cast<max_size_t>(rs1_deps) == res_ROB_index) {
std::cerr << "load rs1" << std::endl;
DEBUG_CERR << "load rs1" << std::endl;
LSQ_queue[last_idx].V1 <= res_value;
LSQ_queue[last_idx].D1 <= 1;
should_monitor_V1 = false;
}
if (should_monitor_V2 && static_cast<max_size_t>(rs2_deps) == res_ROB_index) {
std::cerr << "load rs2" << std::endl;
DEBUG_CERR << "load rs2" << std::endl;
LSQ_queue[last_idx].V2 <= res_value;
LSQ_queue[last_idx].D2 <= 1;
should_monitor_V2 = false;
@ -222,15 +222,15 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
ptr = (ptr + 1) % 32;
}
};
std::cerr << "Load Store Queue is listening data from alu" << std::endl;
DEBUG_CERR << "Load Store Queue is listening data from alu" << std::endl;
if (static_cast<max_size_t>(alu_status_receiver) == 0b10) {
std::cerr << "potentially have sth from alu" << std::endl;
DEBUG_CERR << "potentially have sth from alu" << std::endl;
process_listend_data(static_cast<max_size_t>(completed_aluins_ROB_index),
static_cast<max_size_t>(completed_aluins_result));
}
std::cerr << "Load Store Queue is listening data from memory" << std::endl;
DEBUG_CERR << "Load Store Queue is listening data from memory" << std::endl;
if (static_cast<max_size_t>(mem_data_sign) == 0b10) {
std::cerr << "potentially have sth from memory" << std::endl;
DEBUG_CERR << "potentially have sth from memory" << std::endl;
process_listend_data(static_cast<max_size_t>(completed_memins_ROB_index),
static_cast<max_size_t>(completed_memins_read_data));
}
@ -256,7 +256,7 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
if (((LSQ_queue[head].E1 == 0) || (LSQ_queue[head].E1 == 1 && LSQ_queue[head].D1 == 1)) &&
((LSQ_queue[head].E2 == 0) || (LSQ_queue[head].E2 == 1 && LSQ_queue[head].D2 == 1))) {
// now we can execute the instruction
std::cerr << "Load Store queue is executing instruction" << std::endl;
DEBUG_CERR << "Load Store queue is executing instruction" << std::endl;
next_remain_space++;
can_execute = true;
LSQ_head <= (head + 1) % 32;
@ -319,13 +319,13 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
request_ROB_index <= static_cast<uint32_t>(LSQ_queue[head].ins_ROB_index);
request_address_output <=
(static_cast<uint32_t>(LSQ_queue[head].V1) + static_cast<uint32_t>(LSQ_queue[head].ins_imm));
std::cerr << "\trequest_address_output=" << std::hex << std::setfill('0') << std::setw(8)
DEBUG_CERR << "\trequest_address_output=" << std::hex << std::setfill('0') << std::setw(8)
<< request_address_output.peek() << std::endl;
std::cerr << "\toperand1=" << std::hex << std::setfill('0') << std::setw(8)
DEBUG_CERR << "\toperand1=" << std::hex << std::setfill('0') << std::setw(8)
<< static_cast<uint32_t>(LSQ_queue[head].V1) << std::endl;
std::cerr << "\timm=" << std::hex << std::setfill('0') << std::setw(8)
DEBUG_CERR << "\timm=" << std::hex << std::setfill('0') << std::setw(8)
<< static_cast<uint32_t>(LSQ_queue[head].ins_imm) << std::endl;
std::cerr << "\tROB_index=" << std::dec << static_cast<uint32_t>(LSQ_queue[head].ins_ROB_index)
DEBUG_CERR << "\tROB_index=" << std::dec << static_cast<uint32_t>(LSQ_queue[head].ins_ROB_index)
<< std::endl;
request_data_output <= static_cast<uint32_t>(LSQ_queue[head].V2);
} else {
@ -338,7 +338,7 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
if (!can_execute) request_type_output <= 0;
LSQ_remain_space <= next_remain_space;
LSQ_remain_space_output <= next_remain_space;
std::cerr << "LSQ_queue[16]'s V1: " << std::hex << std::setfill('0') << std::setw(8)
DEBUG_CERR << "LSQ_queue[16]'s V1: " << std::hex << std::setfill('0') << std::setw(8)
<< static_cast<max_size_t>(LSQ_queue[16].V1) << std::endl;
}
};

14
include/memory.h
View File

@ -116,7 +116,7 @@ struct Memory : dark::Module<Memory_Input, Memory_Output, Memory_Private> {
}
}
completed_memins_read_data <= tmp;
std::cerr << "memory read: " << std::hex << std::setfill('0') << std::setw(2) << tmp << " from " << std::hex
DEBUG_CERR << "memory read: " << std::hex << std::setfill('0') << std::setw(2) << tmp << " from " << std::hex
<< static_cast<max_size_t>(cur_opt_addr) << std::endl;
break;
}
@ -129,13 +129,13 @@ struct Memory : dark::Module<Memory_Input, Memory_Output, Memory_Private> {
}
}
completed_memins_read_data <= tmp;
std::cerr << "memory read: " << std::hex << std::setfill('0') << std::setw(4) << tmp << " from " << std::hex
DEBUG_CERR << "memory read: " << std::hex << std::setfill('0') << std::setw(4) << tmp << " from " << std::hex
<< static_cast<max_size_t>(cur_opt_addr) << std::endl;
break;
}
case 4:
completed_memins_read_data <= *reinterpret_cast<uint32_t *>(&memory_data[max_size_t(cur_opt_addr)]);
std::cerr << "memory read: " << std::hex << std::setfill('0') << std::setw(8)
DEBUG_CERR << "memory read: " << std::hex << std::setfill('0') << std::setw(8)
<< *reinterpret_cast<uint32_t *>(&memory_data[max_size_t(cur_opt_addr)]) << " from " << std::hex
<< static_cast<max_size_t>(cur_opt_addr) << std::endl;
break;
@ -188,11 +188,11 @@ struct Memory : dark::Module<Memory_Input, Memory_Output, Memory_Private> {
playback[cur_opt_ROB_index].changes[3].addr <= cur_opt_addr + 3;
playback[cur_opt_ROB_index].changes[3].before <= memory_data[max_size_t(cur_opt_addr) + 3];
*reinterpret_cast<uint32_t *>(&memory_data[max_size_t(cur_opt_addr)]) = max_size_t(cur_opt_data);
std::cerr << "Memory executing sw, ROB_index=" << std::dec
DEBUG_CERR << "Memory executing sw, ROB_index=" << std::dec
<< static_cast<max_size_t>(completed_memins_ROB_index) << std::endl;
std::cerr << "\taddr=" << std::hex << std::setfill('0') << std::setw(8)
DEBUG_CERR << "\taddr=" << std::hex << std::setfill('0') << std::setw(8)
<< static_cast<max_size_t>(cur_opt_addr) << std::endl;
std::cerr << "\tdata=" << std::hex << std::setfill('0') << std::setw(8)
DEBUG_CERR << "\tdata=" << std::hex << std::setfill('0') << std::setw(8)
<< static_cast<max_size_t>(cur_opt_data) << std::endl;
break;
default:
@ -214,7 +214,7 @@ struct Memory : dark::Module<Memory_Input, Memory_Output, Memory_Private> {
cur_opt_data <= data_input;
cur_opt_type <= rw_type;
cur_opt_bytes <= opt_bytes;
std::cerr << "Memory is accepting a request" << std::endl;
DEBUG_CERR << "Memory is accepting a request" << std::endl;
}
max_size_t FetchInstruction(max_size_t addr) { // assume we have a super nb instruction fetch method that can fetch
// an instruction immediately

5
include/register.h
View File

@ -40,8 +40,9 @@ public:
this->_M_new = static_cast<max_size_t>(value);
}
auto peek() const -> max_size_t { // this function should only be used for convinience within the same module
if(this->_M_assigned) return this->_M_new;
return this->_M_old;
// if(this->_M_assigned) return this->_M_new;
// return this->_M_old;
return this->_M_new;
}
explicit operator max_size_t() const { return this->_M_old; }

28
include/registerfile.h
View File

@ -45,8 +45,8 @@ struct RegisterFile : public dark::Module<RegisterFile_Input, RegisterFile_Outpu
// Constructor
}
uint8_t ReturnExitCodeImmediately() {
std::cerr << "Register File: CSU is collecting exit code" << std::endl;
std::cerr << "Sent " << std::dec << (registers[10].peek() & 0xff) << std::endl;
DEBUG_CERR << "Register File: CSU is collecting exit code" << std::endl;
DEBUG_CERR << "Sent " << std::dec << (registers[10].peek() & 0xff) << std::endl;
return registers[10].peek() & 0xff;
}
void work() {
@ -64,12 +64,12 @@ struct RegisterFile : public dark::Module<RegisterFile_Input, RegisterFile_Outpu
}
bool dependency_cleared = false;
if (bool(is_committing)) {
std::cerr << "register file found CSU is committing commit_ins_ROB_index=" << std::dec
DEBUG_CERR << "register file found CSU is committing commit_ins_ROB_index=" << std::dec
<< static_cast<max_size_t>(commit_ins_ROB_index) << std::endl;
if (bool(has_resulting_register)) {
registers[static_cast<max_size_t>(commit_reg_index)] <= commit_reg_value;
if (register_deps[static_cast<max_size_t>(commit_reg_index)] == commit_ins_ROB_index) {
std::cerr << "The dependency is cleared" << std::endl;
DEBUG_CERR << "The dependency is cleared" << std::endl;
if (!(bool(is_issuing) && bool(has_decoded_rd) &&
(static_cast<max_size_t>(decoded_rd) == static_cast<max_size_t>(commit_reg_index))))
register_nodep[static_cast<max_size_t>(commit_reg_index)] <= 1;
@ -87,7 +87,7 @@ struct RegisterFile : public dark::Module<RegisterFile_Input, RegisterFile_Outpu
return;
}
if (bool(is_issuing)) {
std::cerr << "Register File Found CSU is issuing" << std::endl;
DEBUG_CERR << "Register File Found CSU is issuing" << std::endl;
if (bool(has_decoded_rs1)) {
if (static_cast<max_size_t>(decoded_rs1) == 0) {
rs1_deps <= 0;
@ -102,9 +102,9 @@ struct RegisterFile : public dark::Module<RegisterFile_Input, RegisterFile_Outpu
rs1_value <= commit_reg_value;
rs1_nodep <= 1;
}
std::cerr << std::dec << "rs1_deps=" << rs1_deps.peek() << std::endl;
std::cerr << std::hex << std::setw(8) << std::setfill('0') << "rs1_value=" << rs1_value.peek() << std::endl;
std::cerr << "rs1_nodep=" << rs1_nodep.peek() << std::endl;
DEBUG_CERR << std::dec << "rs1_deps=" << rs1_deps.peek() << std::endl;
DEBUG_CERR << std::hex << std::setw(8) << std::setfill('0') << "rs1_value=" << rs1_value.peek() << std::endl;
DEBUG_CERR << "rs1_nodep=" << rs1_nodep.peek() << std::endl;
}
if (bool(has_decoded_rs2)) {
if (static_cast<max_size_t>(decoded_rs2) == 0) {
@ -120,14 +120,14 @@ struct RegisterFile : public dark::Module<RegisterFile_Input, RegisterFile_Outpu
rs2_value <= commit_reg_value;
rs2_nodep <= 1;
}
std::cerr << std::dec << "rs2_deps=" << rs2_deps.peek() << std::endl;
std::cerr << std::hex << std::setw(8) << std::setfill('0') << "rs2_value=" << rs2_value.peek() << std::endl;
std::cerr << "rs2_nodep=" << rs2_nodep.peek() << std::endl;
DEBUG_CERR << std::dec << "rs2_deps=" << rs2_deps.peek() << std::endl;
DEBUG_CERR << std::hex << std::setw(8) << std::setfill('0') << "rs2_value=" << rs2_value.peek() << std::endl;
DEBUG_CERR << "rs2_nodep=" << rs2_nodep.peek() << std::endl;
}
if (bool(has_decoded_rd)) {
std::cerr << "RF: setting rd dependency" << std::endl;
std::cerr << "\tdecoded_rd=" << std::dec << static_cast<max_size_t>(decoded_rd) << std::endl;
std::cerr << "\tissue_ROB_index=" << std::dec << static_cast<max_size_t>(issue_ROB_index) << std::endl;
DEBUG_CERR << "RF: setting rd dependency" << std::endl;
DEBUG_CERR << "\tdecoded_rd=" << std::dec << static_cast<max_size_t>(decoded_rd) << std::endl;
DEBUG_CERR << "\tissue_ROB_index=" << std::dec << static_cast<max_size_t>(issue_ROB_index) << std::endl;
register_deps[static_cast<max_size_t>(decoded_rd)] <= static_cast<max_size_t>(issue_ROB_index);
register_nodep[static_cast<max_size_t>(decoded_rd)] <= 0;
}

30
include/reservestation.h
View File

@ -130,9 +130,9 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
RS_records[deposit_index].E2 <= has_decoded_rs2;
RS_records[deposit_index].D1 <= 1;
RS_records[deposit_index].D2 <= 1;
std::cerr << "Reserve Station has accepted an instruction from CSU" << std::endl;
std::cerr << "\tdeposit_index=" << std::dec << deposit_index << std::endl;
std::cerr << "\tROB_index=" << std::dec << static_cast<max_size_t>(issue_ROB_index) << std::endl;
DEBUG_CERR << "Reserve Station has accepted an instruction from CSU" << std::endl;
DEBUG_CERR << "\tdeposit_index=" << std::dec << deposit_index << std::endl;
DEBUG_CERR << "\tROB_index=" << std::dec << static_cast<max_size_t>(issue_ROB_index) << std::endl;
} else
has_accepted_ins_last_cycle <= 0;
uint32_t last_idx = static_cast<max_size_t>(last_cycle_ins_RS_index);
@ -141,30 +141,30 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
if (bool(has_accepted_ins_last_cycle)) {
// TODO: now dependency info can be read from the register file, in the mean time, CSU will provide the
// potentially missing data
std::cerr << "Reserve Station is listening dependency info from Register File and CSU" << std::endl;
DEBUG_CERR << "Reserve Station is listening dependency info from Register File and CSU" << std::endl;
if (bool(RS_records[last_idx].E1) && bool(rs1_nodep)) {
RS_records[last_idx].V1 <= rs1_value;
RS_records[last_idx].D1 <= 1;
last_cycle_V1_proccessed = true;
std::cerr << "\t Register File: RS1 is not dependent" << std::endl;
DEBUG_CERR << "\t Register File: RS1 is not dependent" << std::endl;
}
if (bool(RS_records[last_idx].E2) && bool(rs2_nodep)) {
RS_records[last_idx].V2 <= rs2_value;
RS_records[last_idx].D2 <= 1;
last_cycle_V2_proccessed = true;
std::cerr << "\t Register File: RS2 is not dependent" << std::endl;
DEBUG_CERR << "\t Register File: RS2 is not dependent" << std::endl;
}
if (bool(RS_records[last_idx].E1) && (!bool(rs1_nodep)) && bool(rs1_is_in_ROB)) {
RS_records[last_idx].V1 <= rs1_in_ROB_value;
RS_records[last_idx].D1 <= 1;
last_cycle_V1_proccessed = true;
std::cerr << "\t ROB: RS1 is in ROB" << std::endl;
DEBUG_CERR << "\t ROB: RS1 is in ROB" << std::endl;
}
if (bool(RS_records[last_idx].E2) && (!bool(rs2_nodep)) && bool(rs2_is_in_ROB)) {
RS_records[last_idx].V2 <= rs2_in_ROB_value;
RS_records[last_idx].D2 <= 1;
last_cycle_V2_proccessed = true;
std::cerr << "\t ROB: RS2 is in ROB" << std::endl;
DEBUG_CERR << "\t ROB: RS2 is in ROB" << std::endl;
}
}
// TODO: now alu, memory may provide data to satisfy the dependency
@ -173,7 +173,7 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
bool should_monitor_V2 =
bool(has_accepted_ins_last_cycle) && bool(RS_records[last_idx].E2) && (!last_cycle_V2_proccessed);
auto process_listend_data = [&](uint32_t res_ROB_index, uint32_t res_value) -> void {
std::cerr << "\tres_ROB_index=" << std::dec << res_ROB_index << std::endl;
DEBUG_CERR << "\tres_ROB_index=" << std::dec << res_ROB_index << std::endl;
for (uint32_t ptr = 0; ptr < 32; ptr++) {
if (RS_records[ptr].state == 0) continue;
if ((!bool(has_accepted_ins_last_cycle)) || ptr != last_idx) {
@ -200,12 +200,12 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
}
}
};
std::cerr << "Reservestation is listening data from ALU" << std::endl;
DEBUG_CERR << "Reservestation is listening data from ALU" << std::endl;
if (static_cast<max_size_t>(alu_status_receiver) == 0b10) {
process_listend_data(static_cast<max_size_t>(completed_aluins_ROB_index),
static_cast<max_size_t>(completed_aluins_result));
}
std::cerr << "Reservestation is listening data from Memory" << std::endl;
DEBUG_CERR << "Reservestation is listening data from Memory" << std::endl;
if (static_cast<max_size_t>(mem_status_receiver) == 0b10) {
process_listend_data(static_cast<max_size_t>(completed_memins_ROB_index),
static_cast<max_size_t>(completed_memins_read_data));
@ -216,12 +216,12 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
if (should_monitor_V1) {
RS_records[last_idx].Q1 <= rs1_deps;
RS_records[last_idx].D1 <= 0;
std::cerr << "\t RS1 depend on ins of ROB index " << std::dec << RS_records[last_idx].Q1.peek() << std::endl;
DEBUG_CERR << "\t RS1 depend on ins of ROB index " << std::dec << RS_records[last_idx].Q1.peek() << std::endl;
}
if (should_monitor_V2) {
RS_records[last_idx].Q2 <= rs2_deps;
RS_records[last_idx].D2 <= 0;
std::cerr << "\t RS2 depend on ins of ROB index " << std::dec << RS_records[last_idx].Q2.peek() << std::endl;
DEBUG_CERR << "\t RS2 depend on ins of ROB index " << std::dec << RS_records[last_idx].Q2.peek() << std::endl;
}
// TODO: now, we can check if we can execute the instruction, memory and L0 cache will listen to this
if (bool(has_accepted_ins_last_cycle)) RS_records[last_idx].state <= 2;
@ -245,11 +245,11 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
if (!can_execute) request_full_id <= 0;
RS_remaining_space <= next_remain_space;
RS_remain_space_output <= next_remain_space;
std::cerr << "Reservestation: next_remain_space=" << std::dec << next_remain_space << std::endl;
DEBUG_CERR << "Reservestation: next_remain_space=" << std::dec << next_remain_space << std::endl;
int tot = 0;
for (int i = 0; i < 32; i++)
if (static_cast<max_size_t>(RS_records[i].state) == 0) tot++;
std::cerr << "\tcurrently there are " << std::dec << tot
DEBUG_CERR << "\tcurrently there are " << std::dec << tot
<< " remain spaces based on state but RS_remaining_space says " << std::dec
<< static_cast<max_size_t>(RS_remaining_space) << std::endl;
if (tot != static_cast<max_size_t>(RS_remaining_space)) {

2
src/main.cpp
View File

@ -170,6 +170,6 @@ int main(int argc, char **argv) {
RWConnect(rf.rs2_deps, rs.rs2_deps);
RWConnect(rf.rs2_value, rs.rs2_value);
// now start running
std::cout << uint32_t(cpu.run(1000, false)) << std::endl;
std::cout << uint32_t(cpu.run(0, false)) << std::endl;
return 0;
}