fix many significant bugs
This commit is contained in:
@ -145,6 +145,8 @@ struct ALU : public dark::Module<ALU_Input, ALU_Output> {
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alu_status <= 0b10;
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result_ROB_index <= request_ROB_index;
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result <= static_cast<max_size_t>(operand1) + imm;
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std::cerr << "\taddi: operand1=" << std::hex << static_cast<max_size_t>(operand1) << " imm=" << std::hex
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<< static_cast<max_size_t>(imm) << " result=" << std::hex << result.peek() << std::endl;
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completed_alu_resulting_PC <= static_cast<max_size_t>(request_PC) + 4;
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return;
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}
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@ -255,6 +255,8 @@ struct CentralScheduleUnit
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commit_has_resulting_register <= record.has_resulting_register;
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commit_reg_index <= record.resulting_register_idx;
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commit_reg_value <= record.resulting_register_value;
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std::cerr << "commit_reg_index=" << std::dec << commit_reg_index.peek() << " commit_reg_value=" << std::hex
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<< std::setw(8) << std::setfill('0') << std::uppercase << commit_reg_value.peek() << std::endl;
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commit_ins_ROB_index <= i;
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actual_PC <= static_cast<max_size_t>(record.resulting_PC);
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if (static_cast<max_size_t>(record.PC_mismatch_mark) == 1) {
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@ -266,6 +268,10 @@ struct CentralScheduleUnit
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halt_signal <= (0b100000000 | static_cast<max_size_t>(a0));
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std::cerr << "halting with code " << std::dec << int(halt_signal.peek()) << std::endl;
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}
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if (record.instruction == 0x1B07A503) {
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std::cerr << "judgeResult loaded from memory is " << std::dec
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<< static_cast<max_size_t>(record.resulting_register_value) << std::endl;
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}
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}
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}
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if (!has_committed) is_committing <= 0;
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@ -331,7 +337,8 @@ struct CentralScheduleUnit
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// can issue
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std::cerr << "csu is issuing mem instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
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<< instruction << " full_ins_id= " << std::hex << std::setw(8) << std::setfill('0')
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<< std::uppercase << full_ins_id << std::endl;
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<< std::uppercase << full_ins_id << " with ROB_index=" << std::dec
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<< static_cast<max_size_t>(ROB_tail) << std::endl;
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is_issuing <= 1;
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has_instruction_issued_last_cycle <= 1;
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uint32_t tail = static_cast<max_size_t>(ROB_tail);
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@ -370,7 +377,8 @@ struct CentralScheduleUnit
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// can issue
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std::cerr << "csu is issuing alu instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
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<< instruction << " full_ins_id= " << std::hex << std::setw(8) << std::setfill('0')
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<< std::uppercase << full_ins_id << std::endl;
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<< std::uppercase << full_ins_id << " with ROB_index=" << std::dec
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<< static_cast<max_size_t>(ROB_tail) << std::endl;
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is_issuing <= 1;
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has_instruction_issued_last_cycle <= 1;
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uint32_t tail = static_cast<max_size_t>(ROB_tail);
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@ -1,5 +1,6 @@
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#pragma once
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#include <cstdint>
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#include <iomanip>
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#include "concept.h"
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#ifndef LOADSTOREQUEUE_H
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#include <array>
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@ -134,6 +135,8 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
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<< static_cast<max_size_t>(has_decoded_rs1) << std::endl;
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std::cerr << "\thas_decoded_rs2: " << std::hex << std::setw(8) << std::setfill('0')
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<< static_cast<max_size_t>(has_decoded_rs2) << std::endl;
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std::cerr << "\tstored in positon " << std::dec << static_cast<max_size_t>(cur_queue_tail) << " of LSQ"
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<< std::endl;
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// LSQ_queue[cur_queue_tail].Q1 <= decoded_rs1; // temporarily, no use
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// LSQ_queue[cur_queue_tail].Q2 <= decoded_rs2; // temporarily, no use
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} else
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@ -156,6 +159,8 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
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LSQ_queue[last_idx].V2 <= rs2_value;
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LSQ_queue[last_idx].D2 <= 1;
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last_cycle_V2_proccessed = true;
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std::cerr << "from register file: LSQ_queue[last_idx].V2=" << std::hex << std::setw(8) << std::setfill('0')
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<< static_cast<max_size_t>(LSQ_queue[last_idx].V2) << std::endl;
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}
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if (bool(LSQ_queue[last_idx].E1) && (!bool(rs1_nodep)) && bool(rs1_is_in_ROB)) {
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LSQ_queue[last_idx].V1 <= rs1_in_ROB_value;
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@ -168,6 +173,8 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
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LSQ_queue[last_idx].V2 <= rs2_in_ROB_value;
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LSQ_queue[last_idx].D2 <= 1;
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last_cycle_V2_proccessed = true;
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std::cerr << "from ROB: LSQ_queue[last_idx].V2=" << std::hex << std::setw(8) << std::setfill('0')
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<< static_cast<max_size_t>(LSQ_queue[last_idx].V2) << std::endl;
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}
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std::cerr << "End of processing dependency information from register file and ROB" << std::endl;
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}
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@ -177,25 +184,36 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
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bool(has_accepted_ins_last_cycle) && bool(LSQ_queue[last_idx].E2) && !last_cycle_V2_proccessed;
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// now alu, memory may provide data to satisfy the dependency
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auto process_listend_data = [&](uint32_t res_ROB_index, uint32_t res_value) -> void {
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std::cerr << "res_ROB_index=" << std::dec << res_ROB_index << std::endl;
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std::cerr << "res_value=" << std::hex << std::setw(8) << std::setfill('0') << res_value << std::endl;
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std::cerr << "rs1_deps=" << std::dec << static_cast<max_size_t>(rs1_deps) << std::endl;
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std::cerr << "rs2_deps=" << std::dec << static_cast<max_size_t>(rs2_deps) << std::endl;
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uint32_t ptr = static_cast<max_size_t>(LSQ_head);
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while (ptr != static_cast<max_size_t>(LSQ_tail)) {
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std::cerr << "\tptr=" << std::dec << ptr << std::endl;
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if ((!bool(has_accepted_ins_last_cycle)) || ptr != last_idx) {
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std::cerr << "\tnormal" << std::endl;
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dark::debug::assert(LSQ_queue[ptr].state == 2, "LSQ_queue[ptr].state != 2");
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if (static_cast<max_size_t>(LSQ_queue[ptr].Q1) == res_ROB_index) {
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if ((!bool(LSQ_queue[ptr].D1)) && static_cast<max_size_t>(LSQ_queue[ptr].Q1) == res_ROB_index) {
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LSQ_queue[ptr].V1 <= res_value;
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LSQ_queue[ptr].D1 <= 1;
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}
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if (static_cast<max_size_t>(LSQ_queue[ptr].Q2) == res_ROB_index) {
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if ((!bool(LSQ_queue[ptr].D2)) && static_cast<max_size_t>(LSQ_queue[ptr].Q2) == res_ROB_index) {
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LSQ_queue[ptr].V2 <= res_value;
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LSQ_queue[ptr].D2 <= 1;
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}
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} else {
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std::cerr << "\timmediately listend data" << std::endl;
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std::cerr << "should_monitor_V1=" << should_monitor_V1 << std::endl;
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std::cerr << "should_monitor_V2=" << should_monitor_V2 << std::endl;
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if (should_monitor_V1 && static_cast<max_size_t>(rs1_deps) == res_ROB_index) {
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std::cerr << "load rs1" << std::endl;
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LSQ_queue[last_idx].V1 <= res_value;
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LSQ_queue[last_idx].D1 <= 1;
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should_monitor_V1 = false;
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}
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if (should_monitor_V2 && static_cast<max_size_t>(rs2_deps) == res_ROB_index) {
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std::cerr << "load rs2" << std::endl;
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LSQ_queue[last_idx].V2 <= res_value;
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LSQ_queue[last_idx].D2 <= 1;
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should_monitor_V2 = false;
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@ -206,11 +224,13 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
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};
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std::cerr << "Load Store Queue is listening data from alu" << std::endl;
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if (static_cast<max_size_t>(alu_status_receiver) == 0b10) {
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std::cerr << "potentially have sth from alu" << std::endl;
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process_listend_data(static_cast<max_size_t>(completed_aluins_ROB_index),
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static_cast<max_size_t>(completed_aluins_result));
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}
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std::cerr << "Load Store Queue is listening data from memory" << std::endl;
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if (static_cast<max_size_t>(mem_data_sign) == 0b10) {
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std::cerr << "potentially have sth from memory" << std::endl;
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process_listend_data(static_cast<max_size_t>(completed_memins_ROB_index),
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static_cast<max_size_t>(completed_memins_read_data));
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}
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@ -237,7 +257,7 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
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((LSQ_queue[head].E2 == 0) || (LSQ_queue[head].E2 == 1 && LSQ_queue[head].D2 == 1))) {
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// now we can execute the instruction
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std::cerr << "Load Store queue is executing instruction" << std::endl;
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next_remain_space--;
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next_remain_space++;
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can_execute = true;
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LSQ_head <= (head + 1) % 32;
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uint32_t ins = static_cast<uint32_t>(LSQ_queue[head].full_ins_id);
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@ -299,6 +319,14 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
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request_ROB_index <= static_cast<uint32_t>(LSQ_queue[head].ins_ROB_index);
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request_address_output <=
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(static_cast<uint32_t>(LSQ_queue[head].V1) + static_cast<uint32_t>(LSQ_queue[head].ins_imm));
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std::cerr << "\trequest_address_output=" << std::hex << std::setfill('0') << std::setw(8)
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<< request_address_output.peek() << std::endl;
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std::cerr << "\toperand1=" << std::hex << std::setfill('0') << std::setw(8)
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<< static_cast<uint32_t>(LSQ_queue[head].V1) << std::endl;
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std::cerr << "\timm=" << std::hex << std::setfill('0') << std::setw(8)
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<< static_cast<uint32_t>(LSQ_queue[head].ins_imm) << std::endl;
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std::cerr << "\tROB_index=" << std::dec << static_cast<uint32_t>(LSQ_queue[head].ins_ROB_index)
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<< std::endl;
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request_data_output <= static_cast<uint32_t>(LSQ_queue[head].V2);
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} else {
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throw std::runtime_error("Invalid instruction");
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@ -310,6 +338,8 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
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if (!can_execute) request_type_output <= 0;
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LSQ_remain_space <= next_remain_space;
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LSQ_remain_space_output <= next_remain_space;
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std::cerr << "LSQ_queue[16]'s V1: " << std::hex << std::setfill('0') << std::setw(8)
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<< static_cast<max_size_t>(LSQ_queue[16].V1) << std::endl;
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}
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};
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} // namespace ZYM
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@ -9,7 +9,7 @@ const static size_t kTotalRegisters = 32;
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struct RegisterFile_Input {
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// receive control signal from CSU
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dark::Wire<1> reset;
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// dark::Wire<1> force_clear_receiver;
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dark::Wire<1> force_clear_receiver;
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dark::Wire<1> is_issuing;
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dark::Wire<1> issue_type;
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dark::Wire<5> issue_ROB_index;
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@ -70,11 +70,22 @@ struct RegisterFile : public dark::Module<RegisterFile_Input, RegisterFile_Outpu
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registers[static_cast<max_size_t>(commit_reg_index)] <= commit_reg_value;
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if (register_deps[static_cast<max_size_t>(commit_reg_index)] == commit_ins_ROB_index) {
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std::cerr << "The dependency is cleared" << std::endl;
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register_nodep[static_cast<max_size_t>(commit_reg_index)] <= 1;
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if (!(bool(is_issuing) && bool(has_decoded_rd) &&
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(static_cast<max_size_t>(decoded_rd) == static_cast<max_size_t>(commit_reg_index))))
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register_nodep[static_cast<max_size_t>(commit_reg_index)] <= 1;
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dependency_cleared = true;
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}
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}
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}
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if (bool(force_clear_receiver)) {
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for (auto ® : register_deps) {
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reg <= 0;
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}
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for (auto ® : register_nodep) {
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reg <= 1;
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}
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return;
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}
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if (bool(is_issuing)) {
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std::cerr << "Register File Found CSU is issuing" << std::endl;
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if (bool(has_decoded_rs1)) {
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@ -1,4 +1,5 @@
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#pragma once
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#include <iterator>
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#include "concept.h"
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#ifndef RESERVATIONSTATION_H
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#include <array>
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@ -88,6 +89,7 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
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RS_remaining_space <= 32;
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RS_remain_space_output <= 32;
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request_full_id <= 0;
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has_accepted_ins_last_cycle <= 0;
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return;
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}
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if (bool(force_clear_receiver)) {
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@ -97,6 +99,7 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
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RS_remaining_space <= 32;
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RS_remain_space_output <= 32;
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request_full_id <= 0;
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has_accepted_ins_last_cycle <= 0;
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return;
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}
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uint32_t next_remain_space = static_cast<max_size_t>(RS_remaining_space);
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@ -127,6 +130,9 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
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RS_records[deposit_index].E2 <= has_decoded_rs2;
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RS_records[deposit_index].D1 <= 1;
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RS_records[deposit_index].D2 <= 1;
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std::cerr << "Reserve Station has accepted an instruction from CSU" << std::endl;
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std::cerr << "\tdeposit_index=" << std::dec << deposit_index << std::endl;
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std::cerr << "\tROB_index=" << std::dec << static_cast<max_size_t>(issue_ROB_index) << std::endl;
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} else
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has_accepted_ins_last_cycle <= 0;
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uint32_t last_idx = static_cast<max_size_t>(last_cycle_ins_RS_index);
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@ -167,15 +173,16 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
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bool should_monitor_V2 =
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bool(has_accepted_ins_last_cycle) && bool(RS_records[last_idx].E2) && (!last_cycle_V2_proccessed);
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auto process_listend_data = [&](uint32_t res_ROB_index, uint32_t res_value) -> void {
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std::cerr << "\tres_ROB_index=" << std::dec << res_ROB_index << std::endl;
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for (uint32_t ptr = 0; ptr < 32; ptr++) {
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if (RS_records[ptr].state == 0) continue;
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if ((!bool(has_accepted_ins_last_cycle)) || ptr != last_idx) {
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dark::debug::assert(RS_records[ptr].state == 2, "RS_records[ptr].state != 2");
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if (static_cast<max_size_t>(RS_records[ptr].Q1) == res_ROB_index) {
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if ((!bool(RS_records[ptr].D1)) && static_cast<max_size_t>(RS_records[ptr].Q1) == res_ROB_index) {
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RS_records[ptr].V1 <= res_value;
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RS_records[ptr].D1 <= 1;
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}
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if (static_cast<max_size_t>(RS_records[ptr].Q2) == res_ROB_index) {
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if ((!bool(RS_records[ptr].D2)) && static_cast<max_size_t>(RS_records[ptr].Q2) == res_ROB_index) {
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RS_records[ptr].V2 <= res_value;
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RS_records[ptr].D2 <= 1;
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}
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@ -191,13 +198,14 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
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should_monitor_V2 = false;
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}
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}
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ptr = (ptr + 1) % 32;
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}
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};
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std::cerr << "Reservestation is listening data from ALU" << std::endl;
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if (static_cast<max_size_t>(alu_status_receiver) == 0b10) {
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process_listend_data(static_cast<max_size_t>(completed_aluins_ROB_index),
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static_cast<max_size_t>(completed_aluins_result));
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}
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std::cerr << "Reservestation is listening data from Memory" << std::endl;
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if (static_cast<max_size_t>(mem_status_receiver) == 0b10) {
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process_listend_data(static_cast<max_size_t>(completed_memins_ROB_index),
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static_cast<max_size_t>(completed_memins_read_data));
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@ -237,6 +245,16 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
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if (!can_execute) request_full_id <= 0;
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RS_remaining_space <= next_remain_space;
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RS_remain_space_output <= next_remain_space;
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std::cerr << "Reservestation: next_remain_space=" << std::dec << next_remain_space << std::endl;
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int tot = 0;
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for (int i = 0; i < 32; i++)
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if (static_cast<max_size_t>(RS_records[i].state) == 0) tot++;
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std::cerr << "\tcurrently there are " << std::dec << tot
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<< " remain spaces based on state but RS_remaining_space says " << std::dec
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<< static_cast<max_size_t>(RS_remaining_space) << std::endl;
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if (tot != static_cast<max_size_t>(RS_remaining_space)) {
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throw std::runtime_error("Reservestation: RS_remaining_space is not consistent with RS_records");
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}
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}
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};
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} // namespace ZYM
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@ -78,7 +78,7 @@ int main(int argc, char **argv) {
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RWConnect(alu.result, csu.completed_aluins_result);
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RWConnect(alu.completed_alu_resulting_PC, csu.completed_alu_resulting_PC);
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// csu <-> register file
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// RWConnect(csu.force_clear_announcer, rf.force_clear_receiver);
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RWConnect(csu.force_clear_announcer, rf.force_clear_receiver);
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RWConnect(csu.is_issuing, rf.is_issuing);
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RWConnect(csu.issue_type, rf.issue_type);
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RWConnect(csu.issue_ROB_index, rf.issue_ROB_index);
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@ -12,7 +12,8 @@
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#ifdef DEBUG
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#define DEBUG_CERR std::cerr
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#else
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#define DEBUG_CERR if(0) std::cerr
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#define DEBUG_CERR \
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if (0) std::cerr
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#endif
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inline uint8_t ReadBit(uint32_t data, int pos) { return (data >> pos) & 1; }
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inline void WriteBit(uint32_t &data, int pos, uint8_t bit) {
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@ -81,7 +82,7 @@ ExecuteFunc Decode(uint32_t instr) {
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}
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uint8_t second_key = funct3 | (funct7 << 3);
|
||||
DEBUG_CERR << "Decoding, opcode=" << std::hex << (int)opcode << " second_key=" << std::dec << (int)second_key
|
||||
<< std::endl;
|
||||
<< std::endl;
|
||||
if (ExecuteFuncMap.find({opcode, second_key}) == ExecuteFuncMap.end()) {
|
||||
throw std::runtime_error("Unsupported instruction");
|
||||
}
|
||||
@ -136,7 +137,7 @@ class RV32IInterpreter {
|
||||
void PrintRegisters() {
|
||||
for (int i = 0; i < 32; i++) {
|
||||
DEBUG_CERR << "x" << i << "=" << std::hex << std::uppercase << std::setw(8) << std::setfill('0') << reg[i]
|
||||
<< std::endl;
|
||||
<< std::endl;
|
||||
}
|
||||
}
|
||||
|
||||
@ -173,7 +174,7 @@ class RV32IInterpreter {
|
||||
memset(reg, 0, sizeof(reg));
|
||||
}
|
||||
bool Fetch() {
|
||||
DEBUG_CERR<<"Fetching PC: "<<std::hex<<PC<<std::endl;
|
||||
DEBUG_CERR << "Fetching PC: " << std::hex << PC << std::endl;
|
||||
IR = *reinterpret_cast<uint32_t *>(&dat[PC]);
|
||||
if (IR == 0x0FF00513) {
|
||||
// DEBUG_CERR<<"ready to exit"<<std::endl;
|
||||
@ -191,10 +192,11 @@ class RV32IInterpreter {
|
||||
while (Fetch()) {
|
||||
// uint8_t opcode=IR&127;
|
||||
// std::cout<<"PC: "<<std::hex<<PC<<std::endl;
|
||||
std::cout << "IR= " << std::hex << std::setw(8) << std::setfill('0') <<std::uppercase<< IR << std::endl;
|
||||
PrintRegisters();
|
||||
Decode(IR)(*this, IR);
|
||||
DEBUG_CERR << std::endl;
|
||||
DEBUG_CERR<<"instruction to Fetch: "<<std::hex<<PC<<std::endl<<std::endl;
|
||||
DEBUG_CERR << "instruction to Fetch: " << std::hex << PC << std::endl << std::endl;
|
||||
}
|
||||
// now set exit_code
|
||||
exit_code = reg[10] & 255;
|
||||
@ -205,40 +207,40 @@ int main() {
|
||||
RV32IInterpreter interpreter;
|
||||
interpreter.LoadProgram(std::cin);
|
||||
interpreter.RunProgram();
|
||||
std::cout <<std::dec<< (int)interpreter.GetExitCode() << std::endl;
|
||||
std::cout << std::dec << (int)interpreter.GetExitCode() << std::endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void Execute_lui(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "lui: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint32_t imm = instruction & 0xFFFFF000;
|
||||
interpreter.reg[rd] = imm;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_auipc(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "auipc: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint32_t imm = instruction & 0xFFFFF000;
|
||||
interpreter.reg[rd] = interpreter.PC + imm;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_jal(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "jal: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint32_t rd = (instruction >> 7) & 31;
|
||||
interpreter.reg[rd] = interpreter.PC + 4;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
uint32_t offset = 0;
|
||||
// 提取并组合立即数
|
||||
WriteBit(offset, 20, ReadBit(instruction, 31));
|
||||
@ -268,7 +270,7 @@ void Execute_jal(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
void Execute_jalr(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "jalr: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint32_t t = interpreter.PC + 4;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -284,13 +286,13 @@ void Execute_jalr(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
interpreter.PC = (interpreter.reg[rs1] + offset_signed) & 0xFFFFFFFE;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
interpreter.reg[rd] = t;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
DEBUG_CERR << "now PC=" << std::hex << interpreter.PC << std::endl;
|
||||
}
|
||||
void Execute_beq(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "beq: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
@ -325,7 +327,7 @@ void Execute_beq(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
void Execute_bne(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "bne: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
@ -360,7 +362,7 @@ void Execute_bne(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
void Execute_blt(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "blt: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
@ -397,7 +399,7 @@ void Execute_blt(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
void Execute_bge(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "bge: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
@ -434,7 +436,7 @@ void Execute_bge(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
void Execute_bltu(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "bltu: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
@ -469,7 +471,7 @@ void Execute_bltu(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
void Execute_bgeu(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "bgeu: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
@ -504,7 +506,7 @@ void Execute_bgeu(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
void Execute_lb(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "lb: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -525,13 +527,13 @@ void Execute_lb(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
}
|
||||
}
|
||||
interpreter.reg[rd] = val;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_lh(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "lh: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -545,20 +547,20 @@ void Execute_lh(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
}
|
||||
int32_t offset_signed = *reinterpret_cast<int32_t *>(&offset);
|
||||
uint32_t addr = interpreter.reg[rs1] + offset_signed;
|
||||
uint32_t val = *(reinterpret_cast<uint16_t*>(&interpreter.dat[addr]));
|
||||
uint32_t val = *(reinterpret_cast<uint16_t *>(&interpreter.dat[addr]));
|
||||
if (ReadBit(val, 15)) {
|
||||
for (int i = 16; i < 32; ++i) {
|
||||
WriteBit(val, i, 1);
|
||||
}
|
||||
}
|
||||
interpreter.reg[rd] = val;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_lw(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "lw: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -572,15 +574,15 @@ void Execute_lw(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
}
|
||||
int32_t offset_signed = *reinterpret_cast<int32_t *>(&offset);
|
||||
uint32_t addr = interpreter.reg[rs1] + offset_signed;
|
||||
uint32_t val = *(reinterpret_cast<uint32_t*>(&interpreter.dat[addr]));
|
||||
uint32_t val = *(reinterpret_cast<uint32_t *>(&interpreter.dat[addr]));
|
||||
interpreter.reg[rd] = val;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_lbu(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "lbu: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -596,13 +598,13 @@ void Execute_lbu(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
uint32_t addr = interpreter.reg[rs1] + offset_signed;
|
||||
uint32_t val = interpreter.dat[addr];
|
||||
interpreter.reg[rd] = val;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_lhu(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "lhu: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -616,15 +618,15 @@ void Execute_lhu(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
}
|
||||
int32_t offset_signed = *reinterpret_cast<int32_t *>(&offset);
|
||||
uint32_t addr = interpreter.reg[rs1] + offset_signed;
|
||||
uint32_t val = *(reinterpret_cast<uint16_t*>(&interpreter.dat[addr]));
|
||||
uint32_t val = *(reinterpret_cast<uint16_t *>(&interpreter.dat[addr]));
|
||||
interpreter.reg[rd] = val;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_sb(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "sb: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
@ -646,7 +648,7 @@ void Execute_sb(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
void Execute_sh(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "sh: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
@ -668,7 +670,7 @@ void Execute_sh(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
void Execute_sw(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "sw: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
@ -684,13 +686,13 @@ void Execute_sw(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
}
|
||||
int32_t offset_signed = *reinterpret_cast<int32_t *>(&offset);
|
||||
uint32_t addr = interpreter.reg[rs1] + offset_signed;
|
||||
*reinterpret_cast<uint32_t *>(&interpreter.dat[addr])=interpreter.reg[rs2];
|
||||
*reinterpret_cast<uint32_t *>(&interpreter.dat[addr]) = interpreter.reg[rs2];
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_addi(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "addi: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -701,13 +703,13 @@ void Execute_addi(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
}
|
||||
}
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] + imm;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_slti(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "slti: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -720,13 +722,13 @@ void Execute_slti(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
int32_t rs1_val = *reinterpret_cast<int32_t *>(&interpreter.reg[rs1]);
|
||||
int32_t signed_imm = *reinterpret_cast<int32_t *>(&imm);
|
||||
interpreter.reg[rd] = rs1_val < signed_imm ? 1 : 0;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_sltiu(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "sltiu: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -739,13 +741,13 @@ void Execute_sltiu(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
uint32_t rs1_val = interpreter.reg[rs1];
|
||||
uint32_t unsigned_imm = imm;
|
||||
interpreter.reg[rd] = rs1_val < unsigned_imm ? 1 : 0;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_xori(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "xori: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -756,7 +758,7 @@ void Execute_xori(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
}
|
||||
}
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] ^ imm;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_ori(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
@ -770,13 +772,13 @@ void Execute_ori(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
}
|
||||
}
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] | imm;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_andi(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "andi: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -787,37 +789,37 @@ void Execute_andi(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
}
|
||||
}
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] & imm;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_slli(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "slli: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t shamt = (instruction >> 20) & 31;
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] << shamt;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_srli(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "srli: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t shamt = (instruction >> 20) & 31;
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] >> shamt;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_srai(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "srai: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -827,50 +829,50 @@ void Execute_srai(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
for (int i = 31; i > 31 - shamt; --i) {
|
||||
WriteBit(interpreter.reg[rd], i, sign_bit);
|
||||
}
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_add(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "add: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] + interpreter.reg[rs2];
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_sub(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "sub: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] - interpreter.reg[rs2];
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_sll(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "sll: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
uint8_t shamt = interpreter.reg[rs2] & 31;
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] << shamt;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_slt(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "slt: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -878,13 +880,13 @@ void Execute_slt(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
int32_t rs1_val = *reinterpret_cast<int32_t *>(&interpreter.reg[rs1]);
|
||||
int32_t rs2_val = *reinterpret_cast<int32_t *>(&interpreter.reg[rs2]);
|
||||
interpreter.reg[rd] = rs1_val < rs2_val ? 1 : 0;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_sltu(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "sltu: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -892,38 +894,38 @@ void Execute_sltu(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
uint32_t rs1_val = interpreter.reg[rs1];
|
||||
uint32_t rs2_val = interpreter.reg[rs2];
|
||||
interpreter.reg[rd] = rs1_val < rs2_val ? 1 : 0;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_xor(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "xor: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] ^ interpreter.reg[rs2];
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_srl(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "srl: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
uint8_t shamt = interpreter.reg[rs2] & 31;
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] >> shamt;
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_sra(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "sra: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
@ -934,30 +936,30 @@ void Execute_sra(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
for (int i = 31; i > 31 - shamt; --i) {
|
||||
WriteBit(interpreter.reg[rd], i, sign_bit);
|
||||
}
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_or(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "or: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] | interpreter.reg[rs2];
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
void Execute_and(RV32IInterpreter &interpreter, uint32_t instruction) {
|
||||
++interpreter.counter;
|
||||
DEBUG_CERR << "executing ins count: " << std::dec << interpreter.counter << " PC= " << std::hex << std::uppercase
|
||||
<< interpreter.PC << std::endl;
|
||||
<< interpreter.PC << std::endl;
|
||||
DEBUG_CERR << "and: instruction=" << std::hex << std::setw(8) << std::setfill('0') << instruction << std::endl;
|
||||
uint8_t rd = (instruction >> 7) & 31;
|
||||
uint8_t rs1 = (instruction >> 15) & 31;
|
||||
uint8_t rs2 = (instruction >> 20) & 31;
|
||||
interpreter.reg[rd] = interpreter.reg[rs1] & interpreter.reg[rs2];
|
||||
interpreter.reg[0]=0;
|
||||
interpreter.reg[0] = 0;
|
||||
interpreter.PC += 4;
|
||||
}
|
||||
Reference in New Issue
Block a user