ZYM/RISC-V-Simulator
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix many significant bugs

Browse Source
This commit is contained in:
ZhuangYumin
2024-08-01 13:50:45 +00:00
parent c7a7524884
commit 90033d5c63
7 changed files with 156 additions and 85 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/alu.h
View File

@ -145,6 +145,8 @@ struct ALU : public dark::Module<ALU_Input, ALU_Output> {
alu_status <= 0b10;
result_ROB_index <= request_ROB_index;
result <= static_cast<max_size_t>(operand1) + imm;
std::cerr << "\taddi: operand1=" << std::hex << static_cast<max_size_t>(operand1) << " imm=" << std::hex
<< static_cast<max_size_t>(imm) << " result=" << std::hex << result.peek() << std::endl;
completed_alu_resulting_PC <= static_cast<max_size_t>(request_PC) + 4;
return;
}

12
include/csu.h
View File

@ -255,6 +255,8 @@ struct CentralScheduleUnit
commit_has_resulting_register <= record.has_resulting_register;
commit_reg_index <= record.resulting_register_idx;
commit_reg_value <= record.resulting_register_value;
std::cerr << "commit_reg_index=" << std::dec << commit_reg_index.peek() << " commit_reg_value=" << std::hex
<< std::setw(8) << std::setfill('0') << std::uppercase << commit_reg_value.peek() << std::endl;
commit_ins_ROB_index <= i;
actual_PC <= static_cast<max_size_t>(record.resulting_PC);
if (static_cast<max_size_t>(record.PC_mismatch_mark) == 1) {
@ -266,6 +268,10 @@ struct CentralScheduleUnit
halt_signal <= (0b100000000 | static_cast<max_size_t>(a0));
std::cerr << "halting with code " << std::dec << int(halt_signal.peek()) << std::endl;
}
if (record.instruction == 0x1B07A503) {
std::cerr << "judgeResult loaded from memory is " << std::dec
<< static_cast<max_size_t>(record.resulting_register_value) << std::endl;
}
}
}
if (!has_committed) is_committing <= 0;
@ -331,7 +337,8 @@ struct CentralScheduleUnit
// can issue
std::cerr << "csu is issuing mem instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
<< instruction << " full_ins_id= " << std::hex << std::setw(8) << std::setfill('0')
<< std::uppercase << full_ins_id << std::endl;
<< std::uppercase << full_ins_id << " with ROB_index=" << std::dec
<< static_cast<max_size_t>(ROB_tail) << std::endl;
is_issuing <= 1;
has_instruction_issued_last_cycle <= 1;
uint32_t tail = static_cast<max_size_t>(ROB_tail);
@ -370,7 +377,8 @@ struct CentralScheduleUnit
// can issue
std::cerr << "csu is issuing alu instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
<< instruction << " full_ins_id= " << std::hex << std::setw(8) << std::setfill('0')
<< std::uppercase << full_ins_id << std::endl;
<< std::uppercase << full_ins_id << " with ROB_index=" << std::dec
<< static_cast<max_size_t>(ROB_tail) << std::endl;
is_issuing <= 1;
has_instruction_issued_last_cycle <= 1;
uint32_t tail = static_cast<max_size_t>(ROB_tail);

36
include/loadstorequeue.h
View File

@ -1,5 +1,6 @@
#pragma once
#include <cstdint>
#include <iomanip>
#include "concept.h"
#ifndef LOADSTOREQUEUE_H
#include <array>
@ -134,6 +135,8 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
<< static_cast<max_size_t>(has_decoded_rs1) << std::endl;
std::cerr << "\thas_decoded_rs2: " << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(has_decoded_rs2) << std::endl;
std::cerr << "\tstored in positon " << std::dec << static_cast<max_size_t>(cur_queue_tail) << " of LSQ"
<< std::endl;
// LSQ_queue[cur_queue_tail].Q1 <= decoded_rs1; // temporarily, no use
// LSQ_queue[cur_queue_tail].Q2 <= decoded_rs2; // temporarily, no use
} else
@ -156,6 +159,8 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
LSQ_queue[last_idx].V2 <= rs2_value;
LSQ_queue[last_idx].D2 <= 1;
last_cycle_V2_proccessed = true;
std::cerr << "from register file: LSQ_queue[last_idx].V2=" << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(LSQ_queue[last_idx].V2) << std::endl;
}
if (bool(LSQ_queue[last_idx].E1) && (!bool(rs1_nodep)) && bool(rs1_is_in_ROB)) {
LSQ_queue[last_idx].V1 <= rs1_in_ROB_value;
@ -168,6 +173,8 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
LSQ_queue[last_idx].V2 <= rs2_in_ROB_value;
LSQ_queue[last_idx].D2 <= 1;
last_cycle_V2_proccessed = true;
std::cerr << "from ROB: LSQ_queue[last_idx].V2=" << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(LSQ_queue[last_idx].V2) << std::endl;
}
std::cerr << "End of processing dependency information from register file and ROB" << std::endl;
}
@ -177,25 +184,36 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
bool(has_accepted_ins_last_cycle) && bool(LSQ_queue[last_idx].E2) && !last_cycle_V2_proccessed;
// now alu, memory may provide data to satisfy the dependency
auto process_listend_data = [&](uint32_t res_ROB_index, uint32_t res_value) -> void {
std::cerr << "res_ROB_index=" << std::dec << res_ROB_index << std::endl;
std::cerr << "res_value=" << std::hex << std::setw(8) << std::setfill('0') << res_value << std::endl;
std::cerr << "rs1_deps=" << std::dec << static_cast<max_size_t>(rs1_deps) << std::endl;
std::cerr << "rs2_deps=" << std::dec << static_cast<max_size_t>(rs2_deps) << std::endl;
uint32_t ptr = static_cast<max_size_t>(LSQ_head);
while (ptr != static_cast<max_size_t>(LSQ_tail)) {
std::cerr << "\tptr=" << std::dec << ptr << std::endl;
if ((!bool(has_accepted_ins_last_cycle)) || ptr != last_idx) {
std::cerr << "\tnormal" << std::endl;
dark::debug::assert(LSQ_queue[ptr].state == 2, "LSQ_queue[ptr].state != 2");
if (static_cast<max_size_t>(LSQ_queue[ptr].Q1) == res_ROB_index) {
if ((!bool(LSQ_queue[ptr].D1)) && static_cast<max_size_t>(LSQ_queue[ptr].Q1) == res_ROB_index) {
LSQ_queue[ptr].V1 <= res_value;
LSQ_queue[ptr].D1 <= 1;
}
if (static_cast<max_size_t>(LSQ_queue[ptr].Q2) == res_ROB_index) {
if ((!bool(LSQ_queue[ptr].D2)) && static_cast<max_size_t>(LSQ_queue[ptr].Q2) == res_ROB_index) {
LSQ_queue[ptr].V2 <= res_value;
LSQ_queue[ptr].D2 <= 1;
}
} else {
std::cerr << "\timmediately listend data" << std::endl;
std::cerr << "should_monitor_V1=" << should_monitor_V1 << std::endl;
std::cerr << "should_monitor_V2=" << should_monitor_V2 << std::endl;
if (should_monitor_V1 && static_cast<max_size_t>(rs1_deps) == res_ROB_index) {
std::cerr << "load rs1" << std::endl;
LSQ_queue[last_idx].V1 <= res_value;
LSQ_queue[last_idx].D1 <= 1;
should_monitor_V1 = false;
}
if (should_monitor_V2 && static_cast<max_size_t>(rs2_deps) == res_ROB_index) {
std::cerr << "load rs2" << std::endl;
LSQ_queue[last_idx].V2 <= res_value;
LSQ_queue[last_idx].D2 <= 1;
should_monitor_V2 = false;
@ -206,11 +224,13 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
};
std::cerr << "Load Store Queue is listening data from alu" << std::endl;
if (static_cast<max_size_t>(alu_status_receiver) == 0b10) {
std::cerr << "potentially have sth from alu" << std::endl;
process_listend_data(static_cast<max_size_t>(completed_aluins_ROB_index),
static_cast<max_size_t>(completed_aluins_result));
}
std::cerr << "Load Store Queue is listening data from memory" << std::endl;
if (static_cast<max_size_t>(mem_data_sign) == 0b10) {
std::cerr << "potentially have sth from memory" << std::endl;
process_listend_data(static_cast<max_size_t>(completed_memins_ROB_index),
static_cast<max_size_t>(completed_memins_read_data));
}
@ -237,7 +257,7 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
((LSQ_queue[head].E2 == 0) || (LSQ_queue[head].E2 == 1 && LSQ_queue[head].D2 == 1))) {
// now we can execute the instruction
std::cerr << "Load Store queue is executing instruction" << std::endl;
next_remain_space--;
next_remain_space++;
can_execute = true;
LSQ_head <= (head + 1) % 32;
uint32_t ins = static_cast<uint32_t>(LSQ_queue[head].full_ins_id);
@ -299,6 +319,14 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
request_ROB_index <= static_cast<uint32_t>(LSQ_queue[head].ins_ROB_index);
request_address_output <=
(static_cast<uint32_t>(LSQ_queue[head].V1) + static_cast<uint32_t>(LSQ_queue[head].ins_imm));
std::cerr << "\trequest_address_output=" << std::hex << std::setfill('0') << std::setw(8)
<< request_address_output.peek() << std::endl;
std::cerr << "\toperand1=" << std::hex << std::setfill('0') << std::setw(8)
<< static_cast<uint32_t>(LSQ_queue[head].V1) << std::endl;
std::cerr << "\timm=" << std::hex << std::setfill('0') << std::setw(8)
<< static_cast<uint32_t>(LSQ_queue[head].ins_imm) << std::endl;
std::cerr << "\tROB_index=" << std::dec << static_cast<uint32_t>(LSQ_queue[head].ins_ROB_index)
<< std::endl;
request_data_output <= static_cast<uint32_t>(LSQ_queue[head].V2);
} else {
throw std::runtime_error("Invalid instruction");
@ -310,6 +338,8 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
if (!can_execute) request_type_output <= 0;
LSQ_remain_space <= next_remain_space;
LSQ_remain_space_output <= next_remain_space;
std::cerr << "LSQ_queue[16]'s V1: " << std::hex << std::setfill('0') << std::setw(8)
<< static_cast<max_size_t>(LSQ_queue[16].V1) << std::endl;
}
};
} // namespace ZYM

15
include/registerfile.h
View File

@ -9,7 +9,7 @@ const static size_t kTotalRegisters = 32;
struct RegisterFile_Input {
// receive control signal from CSU
dark::Wire<1> reset;
// dark::Wire<1> force_clear_receiver;
dark::Wire<1> force_clear_receiver;
dark::Wire<1> is_issuing;
dark::Wire<1> issue_type;
dark::Wire<5> issue_ROB_index;
@ -70,11 +70,22 @@ struct RegisterFile : public dark::Module<RegisterFile_Input, RegisterFile_Outpu
registers[static_cast<max_size_t>(commit_reg_index)] <= commit_reg_value;
if (register_deps[static_cast<max_size_t>(commit_reg_index)] == commit_ins_ROB_index) {
std::cerr << "The dependency is cleared" << std::endl;
register_nodep[static_cast<max_size_t>(commit_reg_index)] <= 1;
if (!(bool(is_issuing) && bool(has_decoded_rd) &&
(static_cast<max_size_t>(decoded_rd) == static_cast<max_size_t>(commit_reg_index))))
register_nodep[static_cast<max_size_t>(commit_reg_index)] <= 1;
dependency_cleared = true;
}
}
}
if (bool(force_clear_receiver)) {
for (auto &reg : register_deps) {
reg <= 0;
}
for (auto &reg : register_nodep) {
reg <= 1;
}
return;
}
if (bool(is_issuing)) {
std::cerr << "Register File Found CSU is issuing" << std::endl;
if (bool(has_decoded_rs1)) {

24
include/reservestation.h
View File

@ -1,4 +1,5 @@
#pragma once
#include <iterator>
#include "concept.h"
#ifndef RESERVATIONSTATION_H
#include <array>
@ -88,6 +89,7 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
RS_remaining_space <= 32;
RS_remain_space_output <= 32;
request_full_id <= 0;
has_accepted_ins_last_cycle <= 0;
return;
}
if (bool(force_clear_receiver)) {
@ -97,6 +99,7 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
RS_remaining_space <= 32;
RS_remain_space_output <= 32;
request_full_id <= 0;
has_accepted_ins_last_cycle <= 0;
return;
}
uint32_t next_remain_space = static_cast<max_size_t>(RS_remaining_space);
@ -127,6 +130,9 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
RS_records[deposit_index].E2 <= has_decoded_rs2;
RS_records[deposit_index].D1 <= 1;
RS_records[deposit_index].D2 <= 1;
std::cerr << "Reserve Station has accepted an instruction from CSU" << std::endl;
std::cerr << "\tdeposit_index=" << std::dec << deposit_index << std::endl;
std::cerr << "\tROB_index=" << std::dec << static_cast<max_size_t>(issue_ROB_index) << std::endl;
} else
has_accepted_ins_last_cycle <= 0;
uint32_t last_idx = static_cast<max_size_t>(last_cycle_ins_RS_index);
@ -167,15 +173,16 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
bool should_monitor_V2 =
bool(has_accepted_ins_last_cycle) && bool(RS_records[last_idx].E2) && (!last_cycle_V2_proccessed);
auto process_listend_data = [&](uint32_t res_ROB_index, uint32_t res_value) -> void {
std::cerr << "\tres_ROB_index=" << std::dec << res_ROB_index << std::endl;
for (uint32_t ptr = 0; ptr < 32; ptr++) {
if (RS_records[ptr].state == 0) continue;
if ((!bool(has_accepted_ins_last_cycle)) || ptr != last_idx) {
dark::debug::assert(RS_records[ptr].state == 2, "RS_records[ptr].state != 2");
if (static_cast<max_size_t>(RS_records[ptr].Q1) == res_ROB_index) {
if ((!bool(RS_records[ptr].D1)) && static_cast<max_size_t>(RS_records[ptr].Q1) == res_ROB_index) {
RS_records[ptr].V1 <= res_value;
RS_records[ptr].D1 <= 1;
}
if (static_cast<max_size_t>(RS_records[ptr].Q2) == res_ROB_index) {
if ((!bool(RS_records[ptr].D2)) && static_cast<max_size_t>(RS_records[ptr].Q2) == res_ROB_index) {
RS_records[ptr].V2 <= res_value;
RS_records[ptr].D2 <= 1;
}
@ -191,13 +198,14 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
should_monitor_V2 = false;
}
}
ptr = (ptr + 1) % 32;
}
};
std::cerr << "Reservestation is listening data from ALU" << std::endl;
if (static_cast<max_size_t>(alu_status_receiver) == 0b10) {
process_listend_data(static_cast<max_size_t>(completed_aluins_ROB_index),
static_cast<max_size_t>(completed_aluins_result));
}
std::cerr << "Reservestation is listening data from Memory" << std::endl;
if (static_cast<max_size_t>(mem_status_receiver) == 0b10) {
process_listend_data(static_cast<max_size_t>(completed_memins_ROB_index),
static_cast<max_size_t>(completed_memins_read_data));
@ -237,6 +245,16 @@ struct ReserveStation : public dark::Module<ReserveStation_Input, ReserveStation
if (!can_execute) request_full_id <= 0;
RS_remaining_space <= next_remain_space;
RS_remain_space_output <= next_remain_space;
std::cerr << "Reservestation: next_remain_space=" << std::dec << next_remain_space << std::endl;
int tot = 0;
for (int i = 0; i < 32; i++)
if (static_cast<max_size_t>(RS_records[i].state) == 0) tot++;
std::cerr << "\tcurrently there are " << std::dec << tot
<< " remain spaces based on state but RS_remaining_space says " << std::dec
<< static_cast<max_size_t>(RS_remaining_space) << std::endl;
if (tot != static_cast<max_size_t>(RS_remaining_space)) {
throw std::runtime_error("Reservestation: RS_remaining_space is not consistent with RS_records");
}
}
};
} // namespace ZYM