ZYM/RISC-V-Simulator
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix many significant bugs

Browse Source
This commit is contained in:
ZhuangYumin
2024-08-01 13:50:45 +00:00
parent c7a7524884
commit 90033d5c63
7 changed files with 156 additions and 85 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
include/loadstorequeue.h
View File

@ -1,5 +1,6 @@
#pragma once
#include <cstdint>
#include <iomanip>
#include "concept.h"
#ifndef LOADSTOREQUEUE_H
#include <array>
@ -134,6 +135,8 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
<< static_cast<max_size_t>(has_decoded_rs1) << std::endl;
std::cerr << "\thas_decoded_rs2: " << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(has_decoded_rs2) << std::endl;
std::cerr << "\tstored in positon " << std::dec << static_cast<max_size_t>(cur_queue_tail) << " of LSQ"
<< std::endl;
// LSQ_queue[cur_queue_tail].Q1 <= decoded_rs1; // temporarily, no use
// LSQ_queue[cur_queue_tail].Q2 <= decoded_rs2; // temporarily, no use
} else
@ -156,6 +159,8 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
LSQ_queue[last_idx].V2 <= rs2_value;
LSQ_queue[last_idx].D2 <= 1;
last_cycle_V2_proccessed = true;
std::cerr << "from register file: LSQ_queue[last_idx].V2=" << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(LSQ_queue[last_idx].V2) << std::endl;
}
if (bool(LSQ_queue[last_idx].E1) && (!bool(rs1_nodep)) && bool(rs1_is_in_ROB)) {
LSQ_queue[last_idx].V1 <= rs1_in_ROB_value;
@ -168,6 +173,8 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
LSQ_queue[last_idx].V2 <= rs2_in_ROB_value;
LSQ_queue[last_idx].D2 <= 1;
last_cycle_V2_proccessed = true;
std::cerr << "from ROB: LSQ_queue[last_idx].V2=" << std::hex << std::setw(8) << std::setfill('0')
<< static_cast<max_size_t>(LSQ_queue[last_idx].V2) << std::endl;
}
std::cerr << "End of processing dependency information from register file and ROB" << std::endl;
}
@ -177,25 +184,36 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
bool(has_accepted_ins_last_cycle) && bool(LSQ_queue[last_idx].E2) && !last_cycle_V2_proccessed;
// now alu, memory may provide data to satisfy the dependency
auto process_listend_data = [&](uint32_t res_ROB_index, uint32_t res_value) -> void {
std::cerr << "res_ROB_index=" << std::dec << res_ROB_index << std::endl;
std::cerr << "res_value=" << std::hex << std::setw(8) << std::setfill('0') << res_value << std::endl;
std::cerr << "rs1_deps=" << std::dec << static_cast<max_size_t>(rs1_deps) << std::endl;
std::cerr << "rs2_deps=" << std::dec << static_cast<max_size_t>(rs2_deps) << std::endl;
uint32_t ptr = static_cast<max_size_t>(LSQ_head);
while (ptr != static_cast<max_size_t>(LSQ_tail)) {
std::cerr << "\tptr=" << std::dec << ptr << std::endl;
if ((!bool(has_accepted_ins_last_cycle)) || ptr != last_idx) {
std::cerr << "\tnormal" << std::endl;
dark::debug::assert(LSQ_queue[ptr].state == 2, "LSQ_queue[ptr].state != 2");
if (static_cast<max_size_t>(LSQ_queue[ptr].Q1) == res_ROB_index) {
if ((!bool(LSQ_queue[ptr].D1)) && static_cast<max_size_t>(LSQ_queue[ptr].Q1) == res_ROB_index) {
LSQ_queue[ptr].V1 <= res_value;
LSQ_queue[ptr].D1 <= 1;
}
if (static_cast<max_size_t>(LSQ_queue[ptr].Q2) == res_ROB_index) {
if ((!bool(LSQ_queue[ptr].D2)) && static_cast<max_size_t>(LSQ_queue[ptr].Q2) == res_ROB_index) {
LSQ_queue[ptr].V2 <= res_value;
LSQ_queue[ptr].D2 <= 1;
}
} else {
std::cerr << "\timmediately listend data" << std::endl;
std::cerr << "should_monitor_V1=" << should_monitor_V1 << std::endl;
std::cerr << "should_monitor_V2=" << should_monitor_V2 << std::endl;
if (should_monitor_V1 && static_cast<max_size_t>(rs1_deps) == res_ROB_index) {
std::cerr << "load rs1" << std::endl;
LSQ_queue[last_idx].V1 <= res_value;
LSQ_queue[last_idx].D1 <= 1;
should_monitor_V1 = false;
}
if (should_monitor_V2 && static_cast<max_size_t>(rs2_deps) == res_ROB_index) {
std::cerr << "load rs2" << std::endl;
LSQ_queue[last_idx].V2 <= res_value;
LSQ_queue[last_idx].D2 <= 1;
should_monitor_V2 = false;
@ -206,11 +224,13 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
};
std::cerr << "Load Store Queue is listening data from alu" << std::endl;
if (static_cast<max_size_t>(alu_status_receiver) == 0b10) {
std::cerr << "potentially have sth from alu" << std::endl;
process_listend_data(static_cast<max_size_t>(completed_aluins_ROB_index),
static_cast<max_size_t>(completed_aluins_result));
}
std::cerr << "Load Store Queue is listening data from memory" << std::endl;
if (static_cast<max_size_t>(mem_data_sign) == 0b10) {
std::cerr << "potentially have sth from memory" << std::endl;
process_listend_data(static_cast<max_size_t>(completed_memins_ROB_index),
static_cast<max_size_t>(completed_memins_read_data));
}
@ -237,7 +257,7 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
((LSQ_queue[head].E2 == 0) || (LSQ_queue[head].E2 == 1 && LSQ_queue[head].D2 == 1))) {
// now we can execute the instruction
std::cerr << "Load Store queue is executing instruction" << std::endl;
next_remain_space--;
next_remain_space++;
can_execute = true;
LSQ_head <= (head + 1) % 32;
uint32_t ins = static_cast<uint32_t>(LSQ_queue[head].full_ins_id);
@ -299,6 +319,14 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
request_ROB_index <= static_cast<uint32_t>(LSQ_queue[head].ins_ROB_index);
request_address_output <=
(static_cast<uint32_t>(LSQ_queue[head].V1) + static_cast<uint32_t>(LSQ_queue[head].ins_imm));
std::cerr << "\trequest_address_output=" << std::hex << std::setfill('0') << std::setw(8)
<< request_address_output.peek() << std::endl;
std::cerr << "\toperand1=" << std::hex << std::setfill('0') << std::setw(8)
<< static_cast<uint32_t>(LSQ_queue[head].V1) << std::endl;
std::cerr << "\timm=" << std::hex << std::setfill('0') << std::setw(8)
<< static_cast<uint32_t>(LSQ_queue[head].ins_imm) << std::endl;
std::cerr << "\tROB_index=" << std::dec << static_cast<uint32_t>(LSQ_queue[head].ins_ROB_index)
<< std::endl;
request_data_output <= static_cast<uint32_t>(LSQ_queue[head].V2);
} else {
throw std::runtime_error("Invalid instruction");
@ -310,6 +338,8 @@ struct LoadStoreQueue : public dark::Module<LoadStoreQueue_Input, LoadStoreQueue
if (!can_execute) request_type_output <= 0;
LSQ_remain_space <= next_remain_space;
LSQ_remain_space_output <= next_remain_space;
std::cerr << "LSQ_queue[16]'s V1: " << std::hex << std::setfill('0') << std::setw(8)
<< static_cast<max_size_t>(LSQ_queue[16].V1) << std::endl;
}
};
} // namespace ZYM