ZYM/RISC-V-Simulator
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fix queue access in csu.h

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This commit is contained in:
ZhuangYumin
2024-08-01 23:43:18 +00:00
parent 00fc4c945e
commit fd92d6df4a
2 changed files with 30 additions and 20 deletions
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2
src/rv32iinterpreter.cpp
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@ -192,7 +192,7 @@ class RV32IInterpreter {
while (Fetch()) {
// uint8_t opcode=IR&127;
// std::cout<<"PC: "<<std::hex<<PC<<std::endl;
std::cout << "IR= " << std::hex << std::setw(8) << std::setfill('0') <<std::uppercase<< IR << std::endl;
std::cout << "csu is committing instruct " << std::hex << std::setw(8) << std::setfill('0') <<std::uppercase<< IR << std::endl;
PrintRegisters();
Decode(IR)(*this, IR);
DEBUG_CERR << std::endl;