ZYM/RISC-V-Simulator
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fix queue access in csu.h

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This commit is contained in:
ZhuangYumin
2024-08-01 23:43:18 +00:00
parent 00fc4c945e
commit fd92d6df4a
2 changed files with 30 additions and 20 deletions
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36
include/csu.h
View File

@ -3,6 +3,7 @@
#include <cstdint>
#include <iostream>
#include "concept.h"
#include "debug.h"
#ifndef CSU_H
#include <array>
#include <functional>
@ -302,6 +303,9 @@ struct CentralScheduleUnit
}
}
record.state <= 3;
DEBUG_CERR << "result collecting for instruct " << std::hex << std::setw(8) << std::setfill('0')
<< std::uppercase << static_cast<max_size_t>(record.instruction) << " with ROB_index=" << std::dec
<< i << std::endl;
}
}
};
@ -335,9 +339,9 @@ struct CentralScheduleUnit
static_cast<max_size_t>(has_instruction_issued_last_cycle);
if (ROB_next_remain_space > 0 && actual_remain_space > 0) {
// can issue
DEBUG_CERR << "csu is issuing mem instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
<< instruction << " full_ins_id= " << std::hex << std::setw(8) << std::setfill('0')
<< std::uppercase << full_ins_id << " with ROB_index=" << std::dec
DEBUG_CERR << "csu is issuing mem instruct " << std::hex << std::setw(8) << std::setfill('0')
<< std::uppercase << instruction << " full_ins_id= " << std::hex << std::setw(8)
<< std::setfill('0') << std::uppercase << full_ins_id << " with ROB_index=" << std::dec
<< static_cast<max_size_t>(ROB_tail) << std::endl;
is_issuing <= 1;
has_instruction_issued_last_cycle <= 1;
@ -375,9 +379,9 @@ struct CentralScheduleUnit
static_cast<max_size_t>(has_instruction_issued_last_cycle);
if (ROB_next_remain_space > 0 && actual_remain_space > 0) {
// can issue
DEBUG_CERR << "csu is issuing alu instruct " << std::hex << std::setw(8) << std::setfill('0') << std::uppercase
<< instruction << " full_ins_id= " << std::hex << std::setw(8) << std::setfill('0')
<< std::uppercase << full_ins_id << " with ROB_index=" << std::dec
DEBUG_CERR << "csu is issuing alu instruct " << std::hex << std::setw(8) << std::setfill('0')
<< std::uppercase << instruction << " full_ins_id= " << std::hex << std::setw(8)
<< std::setfill('0') << std::uppercase << full_ins_id << " with ROB_index=" << std::dec
<< static_cast<max_size_t>(ROB_tail) << std::endl;
is_issuing <= 1;
has_instruction_issued_last_cycle <= 1;
@ -449,34 +453,40 @@ struct CentralScheduleUnit
uint8_t rs2 = static_cast<max_size_t>(this->decoded_rs2);
uint8_t found_rs2 = 0;
uint32_t rs2_v;
for (uint32_t ptr = static_cast<max_size_t>(ROB_head);
ptr != static_cast<max_size_t>(ROB_tail) && (ptr + 1) % kROBSize != static_cast<max_size_t>(ROB_tail);
ptr = (ptr + 1) % kROBSize) {
uint32_t ptr = static_cast<max_size_t>(ROB_head);
dark::debug::assert(static_cast<max_size_t>(ROB_remain_space) < 32, "ROB is empty");
do {
DEBUG_CERR << "\tptr=" << std::dec << ptr << std::endl;
if (ROB_records[ptr].state.peek() == 3) {
DEBUG_CERR << "\tstatus check passed" << std::endl;
if (bool(ROB_records[ptr].has_resulting_register) &&
static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs1) {
rs1_v = ROB_records[ptr].resulting_register_value.peek();
found_rs1 = 1;
DEBUG_CERR << "matching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr << " rs1_v=" << std::hex
<< std::setw(8) << std::setfill('0') << rs1_v << std::endl;
DEBUG_CERR << "\tmatching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr
<< " rs1_v=" << std::hex << std::setw(8) << std::setfill('0') << rs1_v << std::endl;
}
if (bool(ROB_records[ptr].has_resulting_register) &&
static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs2) {
rs2_v = ROB_records[ptr].resulting_register_value.peek();
found_rs2 = 1;
DEBUG_CERR << "\tmatching rs2=" << std::dec << int(rs2) << " ptr=" << std::dec << ptr
<< " rs2_v=" << std::hex << std::setw(8) << std::setfill('0') << rs2_v << std::endl;
}
} else {
if (bool(ROB_records[ptr].has_resulting_register) &&
static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs1) {
found_rs1 = 0;
DEBUG_CERR << "dematching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr << std::endl;
DEBUG_CERR << "\tdematching rs1=" << std::dec << int(rs1) << " ptr=" << std::dec << ptr << std::endl;
}
if (bool(ROB_records[ptr].has_resulting_register) &&
static_cast<max_size_t>(ROB_records[ptr].resulting_register_idx) == rs2) {
found_rs2 = 0;
DEBUG_CERR << "\tdematching rs2=" << std::dec << int(rs2) << " ptr=" << std::dec << ptr << std::endl;
}
}
}
ptr = (ptr + 1) % kROBSize;
} while (ptr != static_cast<max_size_t>(ROB_tail) && (ptr + 1) % kROBSize != static_cast<max_size_t>(ROB_tail));
this->rs1_is_in_ROB <= found_rs1;
this->rs1_in_ROB_value <= rs1_v;
this->rs2_is_in_ROB <= found_rs2;

2
src/rv32iinterpreter.cpp
View File

@ -192,7 +192,7 @@ class RV32IInterpreter {
while (Fetch()) {
// uint8_t opcode=IR&127;
// std::cout<<"PC: "<<std::hex<<PC<<std::endl;
std::cout << "IR= " << std::hex << std::setw(8) << std::setfill('0') <<std::uppercase<< IR << std::endl;
std::cout << "csu is committing instruct " << std::hex << std::setw(8) << std::setfill('0') <<std::uppercase<< IR << std::endl;
PrintRegisters();
Decode(IR)(*this, IR);
DEBUG_CERR << std::endl;