34 lines
1.3 KiB
Markdown
34 lines
1.3 KiB
Markdown
For design and description, see <https://www.wolai.com/zymbox/qsUPoFaTyy88NWHKrjFKtW>
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# RISC-V Simulator Template
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A template which enables you to write verilog-like C++ code.
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## How to use
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Go to [docs/help.md](docs/help.md) for more information.
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## Design
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We propose this template to better simulate the behavior of real hardware.
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That is, register's value will be updated in the next cycle after assigned,
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and wire's value will be updated with respect to the connected register or wire.
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However, it's not easy to synchronize the values of registers and wires in C++ simulation,
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since user may forget to synchronize the value after a cycle is done.
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Therefore, we purpose such a framework, which features automatic value
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synchronization, to help user to write the code in a safer way.
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Since the code is written in C++, IDE will have better code completion
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and highlight support (than Verilog), and user can debug the code with ease.
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In addition, we provide a debug macro control to perform more runtime check
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to help user to debug the code.
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## Deficiencies
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- We do not support Combination Circuit directly now. You may simulate that by simpling using normal integers as intermediate values, and arrange a good order to update the values.
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- We do no support `signed` types now.
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## TODO
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